manisha waje - Academia.edu (original) (raw)

Papers by manisha waje

Advances in intelligent systems and computing, Aug 25, 2016

In the era of emerging trends quantum dot cellular automata has become very popular because of it... more In the era of emerging trends quantum dot cellular automata has become very popular because of its extremely small size. In this paper logically reversible 4 × 4 block is proposed. This block is designed and simulated using Quantum Dot Cellular Automata technology. This QCA based 4 × 4 block named Reversible multifunction block is capable to generate different reversible functions like OR, AND, XOR, XNOR, Full Subtractor, Full Adder, Half Subtractor, Half Adder, code Converters like Gray to Binary and Binary to Gray, Pass Gate, Set, Reset and complement, by changing the inputs at different instants. Reversible Multifunction Block constituted of thirteen reversible functions. Performance analysis of this new design shows that using single block or single Gate, multiple functions can be generated whereas if we wish to design all these functions separately too many number of gates are required. This 4 × 4 reversible Multifunction Block is proved to be efficient in the literature. The proposed design is implemented using QCADesigner 2.3.

2022 International Conference on Smart Generation Computing, Communication and Networking (SMART GENCON)

International Journal of Electrical and Electronics Research

FinFETs are widely used as efficient alternatives to the single gate general transistor in techno... more FinFETs are widely used as efficient alternatives to the single gate general transistor in technology scaling because of their narrow channel characteristic. The width quantization of the FinFET devices helps to reduce the design flexibility of Static Random Access Memory (SRAM) and tackles the design divergence between stable, write and read operations. SRAM is widely used in many medical applications due to its low power consumption but traditional 6T SRAM has short channel effect problems. Recently, to overcome these problems various 7T, 9T, 12T, and 14T SRAM architectures are designed using FinFET. This article provides a comprehensive survey of various designs of SRAM using FinFET. It offers a comparative analysis of FinFET technology, power consumption, propagation delay, power delay product, read and write margin. Additionally, the article presents the simulation of the 5T and 6T SRAM design using CMOS and FinFET for 14 nm technology using Microwind 3.8 simulation tool. The o...

International Journal of Engineering Trends and Technology

2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), 2016

Quantum Dot Cellular automata, one of the emerging nanotechnology is the possible alternative to ... more Quantum Dot Cellular automata, one of the emerging nanotechnology is the possible alternative to these problems. This paper presents the comparative analysis of various QCA methodologies used for the implementation of full adder circuit. Also the designs and performance analysis of QCA full adder using Majority gate, minority gate, multilayer wire crossing, 5 input Majority voter gate is discussed. The designs follow the conventional design approaches, but due to the technology differences, they are modified for the best performance in QCA. The layout and simulation results are presented using QCADesigner Tool. QCADesigner is a QCA layout and simulation tool developed at the University of Calgary [1]. Simulations indicate very attractive performance regarding complexity, area, and delay in Minority gate based full adder and 5 input MV gate based full adder.

2017 International Conference on Inventive Computing and Informatics (ICICI), 2017

Reversible logic has presented with great significance in the recent years because of its charact... more Reversible logic has presented with great significance in the recent years because of its characteristics of reduction in power dissipation. Applications of reversible logic circuits lies in the area of Low power CMOS, quantum computing, nanotechnology, DNA computing etc. Wide range of researchers are currently works on sequential and combinational circuits with the help of reversible logic. Decoders are one of the most significant circuits which are used in combinational logic. Various approaches have been proposed for their design. In this article, we have proposed a design of 2:4 decoder. These proposed circuits will be implemented with the help of CMOS BSIM4 model. Proposed design will be efficient in terms of constant inputs, garbage outputs, quantum cost. The reversible logic based design will be implemented and simulated using tanner EDA tool. Performance analysis of the design will be done considering various parameters.

2020 IEEE Workshop on Evaluation and Beyond - Methodological Approaches to Visualization (BELIV), 2020

Among the many changes brought about by the COVID-19 pandemic, one of the most pressing for scien... more Among the many changes brought about by the COVID-19 pandemic, one of the most pressing for scientific research concerns user testing. For the researchers who conduct studies with human participants, the requirements for social distancing have created a need for reflecting on methodologies that previously seemed relatively straightforward. It has become clear from the emerging literature on the topic and from first-hand experiences of researchers that the restrictions due to the pandemic affect every aspect of the research pipeline. The current paper offers an initial reflection on user-based research, drawing on the authors' own experiences and on the results of a survey that was conducted among researchers in different disciplines, primarily psychology, human-computer interaction (HCI), and visualization communities. While this sampling of researchers is by no means comprehensive, the multidisciplinary approach and the consideration of different aspects of the research pipeline allow us to examine current and future challenges for user-based research. Through an exploration of these issues, this paper also invites others in the VISas well as in the wider-research community, to reflect on and discuss the ways in which the current crisis might also present new and previously unexplored opportunities.

This paper falls inside the extent of execution of Advanced Signal Processing (DSP) calculations ... more This paper falls inside the extent of execution of Advanced Signal Processing (DSP) calculations in the best in class Field Programmable Gate Array (FPGA); along these lines, it shows an FPGA-based inserted framework outline and its assessment for a pre-handling phase of ECG flag investigation; such an outline employments the Discrete Wavelet Transform (DWT) approach. In this way, the framework bargains primarily with the pattern meander ( BLW) evacuation also, the QRS location. As the DWT-based usage requires critical equipment assets, our framework is composed, in a soul of streamlining, to fit in ease and low-control FPGA gadget for convenient restorative hardware. It is created with the Xilinx configuration device, System Generator for DSP which is a module to Simulink. This equipment configuration is tried with ECG information records from the MIT-BIH Arrhythmia database. By a cautious visual examination of the reenactment comes about, we report that the entire outline gives a ...

2015 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT), 2015

In this paper the concept of low power technology and Nanoelectronics is used while implementing ... more In this paper the concept of low power technology and Nanoelectronics is used while implementing the reversible logic based parity checker and parity generator circuits using Quantum Dot Cellular Automata Combination of reversible logic and quantum dot cellular automata technology provides the resultant circuit whose size is extremely small as well as the power consumption in the circuit is very less. In this paper single layered reversible parity generator and checker circuit is proposed. This parity checker and parity generator circuits are designed using efficient reversible XOR gate. Here efficient design of QCA based Feynman gate is used for the implementation of the circuits. In digital communication, a large amount of data is transmitted and received across various mediums. When data is transferred noise gets added to it which makes signal recovery very difficult. Parity bit is used to recover the signal. Parity bit is known as very common error detection code in the data transmission system. Comparative analysis of proposed reversible circuits like Parity Generator and Parity Checker Circuits are efficient in terms of area, complexity and latency and wire crossings. QCADesigner 2.0.3 tool is used for implementation of these circuits.

Advances in Intelligent Systems and Computing, 2019

Artikkelen diskuterer begrepet «maritime samfunn» på bakgrunn av hovedsakelig internasjonal litte... more Artikkelen diskuterer begrepet «maritime samfunn» på bakgrunn av hovedsakelig internasjonal litteratur, som kan gi empiriske, teoretiske og metodiske impulser til norsk lokal-og regionhistorie. Tidsrammen er tidlig nytid, spesielt perioden fra tidlig på 1600-tallet til begynnelsen av 1800-tallet, og eksemplene er hovedsakelig fra kystområdene på Agder og ved Skagerrak. Artikkelen har tre hovedformål: for det første å fremme «maritime samfunn» som en nyttig og viktig kategori i utforskningen og framstillingen av det norske så vel som det internasjonale samfunnet i tidlig nytid; dernest å oppfordre til å tenke på maritime samfunn som et viktig perspektiv i lokal-og regionhistorien; og sist, men ikke minst, å inspirere eller provosere til komparativ forskning på maritime samfunn på tvers av regioner og landegrenser, spesielt rundt Nordsjøen og Skagerrak-Kattegat, hvor utvekslingen av varer, mennesker og ideer har påvirket samfunn i ulike land og regioner.

Solid State Technology, 2020

— In digital VLSI Binary Multiplier is an important part of many units like Arithmetic and Logica... more — In digital VLSI Binary Multiplier is an important part of many units like Arithmetic and Logicalunits, DSP units, image processing and various other application units. Hence it is important to develop alow cost, fast and power efficient multiplier. In this paper we are going to review various Multipliersdesigned with FAs, HAs and with compressor circuits using FinFET technology. Every multiplier has itsown process of partial product generation, partial product reduction and final addition technique. Addersplay vital role in design of multiplier and compressors help to reduce hardware. The important performanceparameters are area, power and delay while designing a multiplier. In this paper we are going to docomparative analysis of these multipliers and exploring their methodology by giving an insight into them.

International journal of scientific research in science, engineering and technology, 2017

Conservative logic is a logic which displays the assets that there's identical range of the i... more Conservative logic is a logic which displays the assets that there's identical range of the inputs in addition to inside the output. It may be reversible or irreversible in nature. Reversibility is not anything but the circuit reveals one-toone mapping between input and output vector, and also represents for each input vector there is an precise output vector and vice versa. Reversibility is specially favoured due to the fact it is able to offer the method for designing low power circuits. Unlike computation mechanisms that contain the switch of electrons, as in CMOS gates, QCA computation does not involve electron switch between adjoining QCA cells. Hence power dissipation could be very less in circuits designed with QCA cells. Therefore it is essential to keep in mind power as an critical parameter during the QCA layout technique. The predominant benefits of this generation are lesser electricity dissipation, advanced velocity and dense systems. In this undertaking layout of r...

2021 IEEE VIS Arts Program (VISAP), 2021

Analog-to-Digital converters are essential building blocks in modern electronic systems. Most of ... more Analog-to-Digital converters are essential building blocks in modern electronic systems. Most of the mixed signal systems today require analog to digital converters and they are being used at the front-end along with DSP applications integrated into one single chip using CMOS technology. Latest VLSI design trend for signal processing system demands high speed operation and less power consumption. A flash ADC architecture is the faster among known ADC architectures, but limited to lower resolution due to large number of components and high power dissipation. So the flash ADC using NMOS Resistor ladder, latched-based comparators, buffer and encoder technique requires. In the digital domain, low power consumption, high speed and low voltage requirements are becoming more important issues these issue solved by use in CMOS technology. The NMOS Resistor ladder, latched-based comparators, buffer and encode technique allows faster ADC. Latched based comparators have been used to provide 6 b...

Human-Computer Interaction – INTERACT 2017, 2017

Living in our information society poses the challenge of having to deal with a plethora of inform... more Living in our information society poses the challenge of having to deal with a plethora of information. While most content is represented through text, keyword extraction and visualization techniques allow the processing and adjustment of text presentation to the readers' individual requirements and preferences. In this paper, we investigate four types of text visualizations and their feasibility to give readers an overview before they actually engage with a text: word clouds, highlighting, mind maps, and image collages. In a user study with 50 participants, we assessed the effects of such visualizations on reading comprehension, reading time, and subjective impressions. Results show that (1) mind maps best support readers in getting the gist of a text, (2) they also give better subjective impressions on text content and structure, and (3) highlighting keywords in a text before reading helps to reduce reading time. We discuss a set of guidelines to inform the design of automated systems for creating text visualizations for reader support.

Adders are of fundamental importance in a wide variety of digital systems. Carry Select Adder (CS... more Adders are of fundamental importance in a wide variety of digital systems. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. A new CMOS logic family called ADIABATIC LOGIC, based on the adiabatic switching principle is presented. In this paper current parameter of carry select adder will be reduced using adiabatic logic which in turn will reduce heat dissipation of the circuit. Proposed work shows better performance in terms of delay, area & power. Simulation & implementation is based on TannerV13 tool with 0.18µm CMOS process technology.