Hamilton Klimach | Universidade Federal do Rio Grande do Sul (original) (raw)

Papers by Hamilton Klimach

This work presents the analysis, design, and performance evaluation of three usual CMOS proportio... more This work presents the analysis, design, and performance evaluation of three usual CMOS proportional to absolute temperature (PTAT) voltage generators, with emphasis on variability effects. Minimization or compensation of the main error sources, such as fabrication variability and intrinsic non-linearities, is an important design challenge required to increase the precision and robustness of a voltage reference. The CMOS PTAT topologies are analytically described and design methodologies for PTAT circuits in subthreshold are presented. The compromises between design conditions and resulting performance are evaluated through simulation for these three PTAT generators, including linearity with temperature, temperature coefficient (TC), and variability impact. Monte-Carlo simulations demonstrated the sensitivity of each topology to fabrication variability, showing that the self-cascode MOSFET structure presents the best accuracy of TC, nominal PTAT voltage, and linearity with temperature.

Analog Integrated Circuits and Signal Processing, Jun 9, 2021

This work presents the design of a low voltage dynamic comparator for low-power ADC applications.... more This work presents the design of a low voltage dynamic comparator for low-power ADC applications. The dynamic comparator uses a pre-amplifier powered by a floating reservoir capacitor and a positive feedback bulk structure. The output stage comprises a simple circuit to reduce the total voltage overhead necessary to define the logic levels. The powering scheme of the pre-amplifier, with a floating reservoir capacitor, contributes to reduce the impacts of global process variability. The positive feedback bulk structure lowers the threshold voltages of the pre-amplifier transistors at the sampling phase. Such structure also provides positive feedback signal during the comparison phase to provide extra transconductance. The proposed dynamic comparator is designed and simulated in a 28 nm CMOS technology and reaches an IRN below of the quantization noise of a 10 bits differential ADCs working with 600 mV power supply. The dynamic comparator achieves 237 μV input-referred noise, while consuming only 38.8 fJ per comparison and having a nominal delay of 5.77 ns.

This paper presents a self-biased self-cascode MOSFET (SBSCM) voltage reference that can operate ... more This paper presents a self-biased self-cascode MOSFET (SBSCM) voltage reference that can operate with supply voltages as low as 0.45 V while consuming tens of pW. The voltage reference is generated through the self-cascode MOSFET (SCM) using transistors with different threshold voltages and is implemented in a way that the SCM itself composes the bias circuitry. The proposed topology was implemented in a standard 0.18 μm CMOS process and post-layout simulation results in a reference voltage of 248 mV with temperature coefficient around 7 ppm/oC for the 0 oC to 125 oC range, while consuming 93 pW at room temperature with 0.45 V of supply voltage. The occupied silicon area is 0.002 mm2.

This work presents the design of a MOS-only voltage reference with nano-watt power consumption. T... more This work presents the design of a MOS-only voltage reference with nano-watt power consumption. The proposed circuit consists of a threshold voltage monitor circuit cascaded with a high-slope proportional to absolute temperature (PTAT) voltage generator. The operation of the circuit is analytically described and a design methodology is presented. The proposed circuit was designed and simulated in a standard 130 nm CMOS process while consuming just 37 nW under 1.2 V of power supply at room temperature. Simulation results present a 585 mV reference voltage with a typical temperature coefficient (TC) of 10.13 ppm/°C, for a temperature range from −40 to 125 °C, a power supply rejection ratio (PSRR) of −54.41 dB at 100 Hz, and a line sensitivity of 0.071 %/V was found for a supply range from 1 V to 1.8 V. Monte-Carlo simulations are presented to evaluate the sensitivity to fabrication variability. The estimated silicon area is 0.0078 mm2.

This work presents a low voltage dynamic comparator for low-power ADC applications. The dynamic c... more This work presents a low voltage dynamic comparator for low-power ADC applications. The dynamic comparator uses a pre-amplifier powered by a floating reservoir capacitor and bulk-driven structure. The latch stage is done by a simple circuit to reduce the total voltage overhead necessary to define the logic levels and uses a charge sharing technique in order to reduce the energy consumption per conversion. The floating reservoir capacitor powered pre-amplifier reduces the impacts of global process variability and improves the input common-mode voltage performance. The bulk-driven structure lowers the threshold voltages of the pre-amplifier transistors at the sampling phase. Such structure also works as a positive feedback signal during the comparison phase to provide extra transconductance. The proposed dynamic comparator is designed and simulated in 28nm CMOS technology and reaches a performance suitable for 8 bits ADCs working with 600mV power supply. The dynamic comparator achieves 380μV input-referred noise, while consuming only 40 fJ per comparison and having a nominal delay of 2.26ns.

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)

2020 IEEE International Conference on RFID (RFID), 2020

This paper presents a non-linear shunt regulator based on a PWM RF power detector for RFID applic... more This paper presents a non-linear shunt regulator based on a PWM RF power detector for RFID applications. The shunt regulator is composed of two feedback loops. The first is a fast loop based on a simple RF voltage clamp that guarantees overvoltage protection for the internal circuits. The second is an accurate loop based on a power detector circuit that slowly corrects the first loop errors according to the input RF power. The theoretical formulation of the RF-to-DC conversion in the power detector is presented and compared to a high-level implementation. A small-signal model of the complete shunt regulator was developed to assist in the CMOS circuit design. The regulator is part of a commercial low-frequency RFID transponder. It shows an improvement of 16.7 % in the maximum communication distance of the transponder with the shunt regulator enabled when compared to the previous power limiting approach using only clamping diodes.

2017 15th IEEE International New Circuits and Systems Conference (NEWCAS), 2017

This work presents a fully integrated single-stage 2.4 GHz power amplifier (PA) that was designed... more This work presents a fully integrated single-stage 2.4 GHz power amplifier (PA) that was designed in a 180nm CMOS process using a power combining technique to achieve higher output power. A series combining transformer (SCT) combines two cascode differential amplifiers and makes extensive use of virtual AC ground nodes to reduce the impact of bond-wire parasitics. The center-taps of the output transformers are used for 2nd harmonic impedance tuning inside the chip. In post-layout simulation the PA uses a 3.3 V power supply and achieves 24dBm maximum output power at a peak drain efficiency of 23.4%. The test chip returned recently from fabrication and it will undergo electrical tests soon.

Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Internet of Things (IoT) is a topic of growing interest and intensive research in industry, techn... more Internet of Things (IoT) is a topic of growing interest and intensive research in industry, technological centers and academy, where data communication is one of its most relevant aspects. Since IoT is an open field for new applications, it does not have yet a standard communication protocol. This paper presents the system level design of a WiFi receiver supporting the novel low power standard IEEE 802.11ah with focus on IoT applications. Theoretical performance analysis as well as system level design strategies are presented. Individual blocks of the receiver chain are specified as a condition for future circuit-level design. Simulation results validate the proposed system specifications attending the 802.11ah standard. The presented receiver provides 80.5dB maximum gain, 9 dB minimum noise figure and 69.4 dB of dynamic range. Those performance parameters lead to −99.4 dBm sensitivity, 21 dB and 51 dB for adjacent and non-adjacent maximum channel rejection.

IEEE Transactions on Circuits and Systems II: Express Briefs, 2021

An ultra-low voltage and ultra-low power Digital-Based Operational Transconductance Amplifier (DB... more An ultra-low voltage and ultra-low power Digital-Based Operational Transconductance Amplifier (DB-OTA) is presented and demonstrated on silicon in 180 nm CMOS. The DB-OTA is designed using digital standard cells, hence benefitting from technology scaling as much as digital circuits, while also being technology- and design-portable, and requiring minimal design and integration effort compared to conventional analog-intensive OTAs. The fabricated DB-OTA testchip occupies a compact area of 1,426 mutextm2\mu \text{m}^{2}mutextm2 , operates at supply voltages down to 300 mV, and consumes only 590 pW while driving a capacitive load of 80pF. Its measured Total Harmonic Distortion (THD) is lower than 5% at a 100-mV input signal swing. Based on these results, the proposed DB-OTA achieves 2,101 V−1 small-signal figure of merit (FOMS) and 1,070 large-signal figure of merit (FOML). To the best of the authors’ knowledge, the power is the lowest reported to date in an OTA, and the achieved figures of merit are the best in sub-500 mV OTAs reported to date. The low cost, the low design effort and the high power efficiency of DB-OTA make it well suited for purely harvested low-frequency analog interfaces in sensor nodes.

IEEE Transactions on Circuits and Systems II: Express Briefs, 2019

A voltage reference based on MOSFETs operated under Zero Temperature Coefficient (ZTC) bias is pr... more A voltage reference based on MOSFETs operated under Zero Temperature Coefficient (ZTC) bias is proposed. The circuit operates in a power supply voltage range from 0.3V up to 1.2V and outputs three different reference voltages using Standard-V T (SVT), Low-V T (LVT), and Zero-V T (ZVT) MOS transistors biased near their ZTC point by a single PTAT current reference. Measurements on 15 circuit samples fabricated in a standard 0.13-µm CMOS process show a worst-case normalized standard deviation (σ/µ) of 3% (SVT), 5.1% (LVT) and 10.8% (ZVT) respectively with a 75% of confidence level. At the nominal supply voltage of 0.45 V, the measured effective temperature coefficients (TC eff) range from 140 to 200 ppm/ o C over the full commercial temperature range. At room temperature (25 o C), line sensitivity in the ZVT VR is just 1.3%/100mV, over the whole supply range. The proposed reference draws around 5 µW and occupies 0.014 mm 2 of silicon area.

2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI), 2016

A low-voltage high-PSRR CMOS voltage reference operating with picowatt power consumption is prese... more A low-voltage high-PSRR CMOS voltage reference operating with picowatt power consumption is presented. The voltage reference is generated from the threshold voltage (VT) difference of two transistors biased in weak inversion. The VT difference is achieved through its dependence with the transistor dimensions. The high-PSRR is obtained using zero-VT transistors as active loads. The final circuit was designed in a 130 nm CMOS process and occupies around 0.0007 mm2 of silicon area while consuming just 18.5 pW at 27°C. Post-layout simulations present a 62 mV reference voltage with a temperature coefficient of 15 ppm/°C, for a temperature range from -25 to 125 °C and a Power Supply Rejection Ratio (PSRR) of -68.7 dB at 0.3 V of supply voltage.

2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS), 2016

In this work a novel resistorless MOSFET 3-transistor voltage reference that operates in the pico... more In this work a novel resistorless MOSFET 3-transistor voltage reference that operates in the picowatt range and occupies very small area is proposed. The circuit is based on a self-cascode structure that is biased in subthreshold condition using the leakage current provided by a reverse biased MOSFET diode. Its electrical behavior is analytically described and a design methodology is presented to allow the transistors sizing for optimal temperature compensation. Simulation results for a standard 130 nm CMOS process are presented to validated the proposed circuit topology. A reference voltage of 85 mV is obtained with a temperature coefficient (TC) of 17.4 ppm/°C and consuming only 7 pW under 0.3 V of power supply at room temperature. Monte Carlo analysis shows that the reference voltage σ/μ<; 3.3% and that 90% of the samples present TC<;50 ppm/°C without trimming.

2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)

2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2019

This paper presents a power-efficient Ultra Low Voltage (ULV) Digital-Based Operational Transcond... more This paper presents a power-efficient Ultra Low Voltage (ULV) Digital-Based Operational Transconductance Amplifier (DB-OTA), which uses static logic gates and processes digitally the analog input signal. Post-layout simulations in 180nm CMOS technology show that at 300mV supply voltage the circuit consumes just 2nW while driving a capacitive load of 80pF with Total Harmonic Distortion lower than 5% at 100mV input signal swing. The total silicon area is 1,426 µm 2. The maximum energy efficiency supply for the DB-OTA and its scalability to 40nm CMOS technology node are also demonstrated.

2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS), 2017

This work presents a six phase Switched Capacitor (SC) DC — DC converter for photovoltaic Energy ... more This work presents a six phase Switched Capacitor (SC) DC — DC converter for photovoltaic Energy Harvesting designed in a 130 nm CMOS process for commercial motes application and Internet of Things (IoT). It tracks the Maximum Power Point (MPP) of a commercial 3 cm × 3 cm 60 mW poly-crystalline photoelectric panel through switching frequency modulation aiming battery recharge. Open-circuit voltage ratio was the chosen Maximum Power Point Tracking (MPPT) strategy. The converter achieves a maximum power conversion efficiency of 90 % for input power higher than 30 mW and is designed to operate with input voltages from 1.25 V to 1.8 V, resulting output voltages from 2.5 V to 3.6 V, respectively. Peripheral circuitry also includes an output over-voltage protection of 3.6 V and the control circuits, that consumes a total of 850 μA at 3.3 V. Complete layout consumes 300 × 700 μm2 of silicon area. The only external components are 6×100 nF capacitors.

Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)

IEEE Access

This paper presents the operation principle and the silicon characterization of a power efficient... more This paper presents the operation principle and the silicon characterization of a power efficient ultra-low voltage and ultra-low area fully-differential, digital-based Operational Transconductance Amplifier (OTA), suitable for microscale biosensing applications (BioDIGOTA). Measured results in 180nm CMOS prototypes show that the proposed BioDIGOTA is able to work with a supply voltage down to 400 mV, consuming only 95 nW. Owing to its intrinsically highly-digital feature, the BioDIGOTA layout occupies only 0.022 mm 2 of total silicon area, lowering the area by 3.22× times compared to the current state of the art, while keeping reasonable system performance, such as 7.6 NEF with 1.25 µV RMS input referred noise over a 10 Hz bandwidth, 1.8% of THD, 62 dB of CMRR and 55 dB of PSRR. INDEX TERMS Ultra-low voltage (ULV) CMOS, ultra-low power (ULP), operational transconductance amplifier (OTA), digital-based circuit, the Internet of Things (IoT).