Gian Domenico Licciardo | University of Salerno Italy (original) (raw)

Papers by Gian Domenico Licciardo

Research paper thumbnail of Polymer Insulator Processing‐Organic Transistor Performance Relationship Investigated through Admittance Spectroscopy

Macromolecular Symposia

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Research paper thumbnail of Design and FPGA implementation of a real-time processor for the HDR conversion of images and videos

2016 8th Computer Science and Electronic Engineering (CEEC)

In this paper a multiresolution architecture to expand the dynamic range of low dynamic range (LD... more In this paper a multiresolution architecture to expand the dynamic range of low dynamic range (LDR) images to 32-bit high dynamic range (HDR) counterpart is presented. The processor is capable to provide on-the-fly calculation of the edge-preserving bilateral filtering and luminance average, to images images up to full-HD images (1920×1080 pixels) using 25×9 filtering and up to 4K UHDTV images (3840×2160 pixels) using 25×5 filtering without frame buffers. To this end, a “hardware friendly” algorithm has been derived from the most effective methods presented in the literature. Additionally, the proposed design is capable of processing the input pixel in streaming order, as they come from input devices by avoiding frame buffers and eliminating external DRAM. The processor complexity can be configured with different area/speed ratios in order to meet the requirements of different FPGA platforms. Implemented on a high-end FPGA the processor achieves state-of-the art performances.

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Research paper thumbnail of Losses of 4H-SiC DMOFET in high voltage power converters

2017 IEEE International Conference on Environment and Electrical Engineering and 2017 IEEE Industrial and Commercial Power Systems Europe (EEEIC / I&CPS Europe), 2017

Power converter efficiency strongly depends on active device performance and, in this paper, we c... more Power converter efficiency strongly depends on active device performance and, in this paper, we compare static and dynamic Figure-Of-Merits in terms of the electrical parameters in order to understand which are the actual limits of 4H-SiC DMOSFETs. Basing on a novel analytical model of 4H-SiC DMOSFET, we will show the maximum performances available on this technology. Data of commercial available devices are also compared so that we can understand the state-of-art of such power transistors. Finally, we propone a new Figure-of-merit which takes into account dynamic and static performances and permits to compare power DMOSFETs with different electrical characteristics and different geometries.

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Research paper thumbnail of Low-power Design of a Gravity Rotation Module for HAR Systems Based on Inertial Sensors

2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2018

In this paper, for the first time the design of a HW module to eliminate the effect of the gravit... more In this paper, for the first time the design of a HW module to eliminate the effect of the gravity acceleration from data acquired from inertial sensors is presented. A new “hardware friendly” algorithm has been derived from the Rodrigues' rotation formula, which can be implemented in a more compact iterative structure. By exploiting 32-bit floating-point arithmetic, the design is able to combine high accuracy and low power requirements needed by any intelligent Human Activity Recognition system, based on artificial neural networks. Synthesis with 65 nm CMOS std _cells returns a power dissipation below 2 μ W and an area of about 0.05 mm2, Results are the current state-of-the-art for this kind of system and they are very promising for the future integration in smart sensors for wearable applications.

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Research paper thumbnail of Evaluation of NB-PLC in railway environments

2017 IEEE International Conference on Environment and Electrical Engineering and 2017 IEEE Industrial and Commercial Power Systems Europe (EEEIC / I&CPS Europe), 2017

In this paper, the possibility to use Narrow-Band Power-Line Communication (NB-PLC), based on PRI... more In this paper, the possibility to use Narrow-Band Power-Line Communication (NB-PLC), based on PRIME and G3-PLC protocols, in a particular harsh environment is demonstrated, with the purpose to significantly reduce the cable infrastructure and the related costs. To this end, the performances of a NB-PLC system have been measured when it is used in conjunction with an a.c. single phase power-line that delivers energy to the light signals in a railway environment. The context is very representative, since the lights in a terminal station and, hence, their controlling signals must obey to severe security standards and operate in a very harsh environment, populated by many electromagnetic interferences of several typologies, power sources and drain nodes. A testbed has been built, composed by the power generation core, the PLC modems and a cable long up to 2250m. Performance in terms of PSNR, RS SI, Throughput and BER have been reported for the entire modulation scheme that the PLC proto...

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Research paper thumbnail of Novel Advanced Analytical Design Tool for 4H-SiC VDMOSFET Devices

Materials Science Forum, 2017

An analytical tool to design 4H-SiC power vertical Double-diffused Metal-Oxide-Semiconductor Fiel... more An analytical tool to design 4H-SiC power vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect-Transistor is proposed. The model optimizes, in terms of the doping concentration in the Drift–region, the trade–off between the ON–resistance, RON, and the maximum blocking voltage, VBL, that is the Drain-Source voltage for which the avalanche breakdown appears at the p+–well/n-DRIFT junction together with the breakdown of the Gate oxide. Finding such trade-off means to maximize, Figure-Of-Merit. Our results are based on a novel full–analytical model of the electric field in the Gate oxide, EOX, whose generality is ensured by the absence of fitting and empirical parameters. Model results are successfully compared with 2D–simulations covering a wide range of device performances.

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Research paper thumbnail of Stream Processor for Real-Time Inverse Tone Mapping of Full-HD Images

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015

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Research paper thumbnail of Modeling of an Organic Thin Film Transistor as Temperature Sensor

Lecture notes in electrical engineering, Jun 29, 2022

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Research paper thumbnail of Quantized ID-CNN for a Low-power PDM-to-PCM Conversion in TinyML KWS Applications

2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS)

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Research paper thumbnail of Quantized Fully Convolution Neural Network for HW Implementation of Human Posture Recognition

2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS)

In this paper, a very tiny HW design of a Quantized Fully Convolutional Neural Network is propose... more In this paper, a very tiny HW design of a Quantized Fully Convolutional Neural Network is proposed which demonstrates that accurate Human Posture Recognition can be designed by exploiting only pressure sensors and keeping the computation close to the data sources, according to the edge computing paradigm. The custom design of the QFCN exploits a base-2 quantization scheme to achieve state-of-the-art performances in terms of classification accuracy, together with a very reduced number of mapped physical resources and power consumption. Trained and validated on a public dataset for in-bed posture classification, the QFCN exhibits an accuracy up to 96.77% in recognizing 17 different postures. When prototyped on a Xilinx Artix 7 FPGA the design achieves less than 7 mW dynamic power dissipation and a maximum operation frequency of 26.6 MHz, compatible with an Output Data Rate (ODR) of the sensors of 9.13 kHz.

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Research paper thumbnail of Memory analysis of Interest Point Detector and Compact Descriptor algorithms

This document encloses analysis of portions of extraction module as composed by Difference of Gau... more This document encloses analysis of portions of extraction module as composed by Difference of Gaussian Interest Point Detector (DoG), Scale Invariant Feature Transform (SIFT) and Compressed Histogram of Gradients (ChoG) algorithms. With reference to TMuC, the Keypoint Selection, the Vector Quantization, and the Entropy Encoding were not considered in this analysis. The analysis, altought not fully completed, was mainly focused on the memory requirements and the feasibility of the system

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Research paper thumbnail of A Model of the V-T Characteristics for an OTFT Temperature Sensor

2021 International Semiconductor Conference (CAS), 2021

An analytical model, able to describe the temperature dependence of the electrical characteristic... more An analytical model, able to describe the temperature dependence of the electrical characteristics of an organic thin film transistor (OTFT), is derived from the multiple trapping and release (MTR) theory related to an exponential distribution of tail states in the organic semiconductor layer at the insulator interface. The aim is to investigate the origin of the linearity of a temperature sensor based on a diode-connected OTFT, exhibiting a linearity of 99.93% and a sensitivity of about 110 mV/K, exceeding that of silicon-based sensors, when biased with a current of 16 nA. The model shows that the linear behavior is given by the compensation of two non-linear functions of temperature, one depending on the OTFT flat-band voltage, the other, varying with the bias current, on the interface state distribution.

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Research paper thumbnail of Feasibility of 4H-SiC p-i-n Diode for Sensitive Temperature Measurements Between 20.5 K and 802 K

IEEE Sensors Journal, 2019

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Research paper thumbnail of Multiplier-Less Stream Processor for 2D Filtering in Visual Search Applications

IEEE Transactions on Circuits and Systems for Video Technology, 2016

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Research paper thumbnail of Design of an offset-tolerant VSA bit-line sensing circuit for SRAM memories

Electronics Letters, 2016

The design of a new bit-line sensing scheme of SRAM memories is presented, which combines offset ... more The design of a new bit-line sensing scheme of SRAM memories is presented, which combines offset cancellation and compensation solutions. FCMOS inverters, brought to operate in their maximum gain region, are used to compensate the systematic offset of the sense amplifier and reduce the sensing delay. Systematic offset of the inverter amplifiers is cancelled by means of equalising feedback connections. A simulation analysis in Cadence environment and TSMC PDK demonstrates the very good potential of the proposed solution when it is compared with the recent and the established literature.

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Research paper thumbnail of Physical model, measurement setup and experiments of a measurement technique of the carrier lifetime profile in power devices

2007 International Workshop on Physics of Semiconductor Devices, 2007

In this paper the physical model of a recently proposed technique to measure the spatial distribu... more In this paper the physical model of a recently proposed technique to measure the spatial distribution of the majority and minority carrier lifetime along silicon epilayers is presented. The model, verified by numerical simulations, clarifies the behaviour of the test structure used in the technique and gives a physical interpretation of the measured quantities. Experimental measurements are also presented, performed by using a measurement setup which ensures correct and noiseless results.

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Research paper thumbnail of A self-consistent model of the static and switching behaviour of 4H-SiC diodes

CAS 2010 Proceedings (International Semiconductor Conference), 2010

A novel model which is capable of describing with significant accuracy the temporal-spatial distr... more A novel model which is capable of describing with significant accuracy the temporal-spatial distributions of the minority carriers in 4H-SiC p-i-n diodes is presented. The analytical behaviour of the current, voltage and carrier distributions is compared with numerical simulations and with experimental results.

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Research paper thumbnail of Experimental measurements of majority and minority carrier lifetime profile in SI epilayers by the use of an improved OCVD method

IEEE Electron Device Letters, 2005

In this letter, the first experimental results of a recently proposed technique for measuring the... more In this letter, the first experimental results of a recently proposed technique for measuring the carrier lifetime profile are presented. The technique makes use of a four-terminal bipolar test structure to electrically define the epilayer volume where recombination occurs and employs the open circuit voltage decay method for lifetime parameters extraction. For the capability of the test structure to depurate

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Research paper thumbnail of CDVS: STM Detector Hw accelerator feasibility study and demonstrator

In order to validate feasibility of HW acceleration for interest point detection, one of the most... more In order to validate feasibility of HW acceleration for interest point detection, one of the most computational intensive part of the CDVS pipeline, STM has designed and implemented on FPGA a draft HW accelerator IP and demonstration is provided

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Research paper thumbnail of Low Power Tiny Binary Neural Network with improved accuracy in Human Recognition Systems

2020 23rd Euromicro Conference on Digital System Design (DSD)

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Research paper thumbnail of Polymer Insulator Processing‐Organic Transistor Performance Relationship Investigated through Admittance Spectroscopy

Macromolecular Symposia

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Research paper thumbnail of Design and FPGA implementation of a real-time processor for the HDR conversion of images and videos

2016 8th Computer Science and Electronic Engineering (CEEC)

In this paper a multiresolution architecture to expand the dynamic range of low dynamic range (LD... more In this paper a multiresolution architecture to expand the dynamic range of low dynamic range (LDR) images to 32-bit high dynamic range (HDR) counterpart is presented. The processor is capable to provide on-the-fly calculation of the edge-preserving bilateral filtering and luminance average, to images images up to full-HD images (1920×1080 pixels) using 25×9 filtering and up to 4K UHDTV images (3840×2160 pixels) using 25×5 filtering without frame buffers. To this end, a “hardware friendly” algorithm has been derived from the most effective methods presented in the literature. Additionally, the proposed design is capable of processing the input pixel in streaming order, as they come from input devices by avoiding frame buffers and eliminating external DRAM. The processor complexity can be configured with different area/speed ratios in order to meet the requirements of different FPGA platforms. Implemented on a high-end FPGA the processor achieves state-of-the art performances.

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Research paper thumbnail of Losses of 4H-SiC DMOFET in high voltage power converters

2017 IEEE International Conference on Environment and Electrical Engineering and 2017 IEEE Industrial and Commercial Power Systems Europe (EEEIC / I&CPS Europe), 2017

Power converter efficiency strongly depends on active device performance and, in this paper, we c... more Power converter efficiency strongly depends on active device performance and, in this paper, we compare static and dynamic Figure-Of-Merits in terms of the electrical parameters in order to understand which are the actual limits of 4H-SiC DMOSFETs. Basing on a novel analytical model of 4H-SiC DMOSFET, we will show the maximum performances available on this technology. Data of commercial available devices are also compared so that we can understand the state-of-art of such power transistors. Finally, we propone a new Figure-of-merit which takes into account dynamic and static performances and permits to compare power DMOSFETs with different electrical characteristics and different geometries.

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Research paper thumbnail of Low-power Design of a Gravity Rotation Module for HAR Systems Based on Inertial Sensors

2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2018

In this paper, for the first time the design of a HW module to eliminate the effect of the gravit... more In this paper, for the first time the design of a HW module to eliminate the effect of the gravity acceleration from data acquired from inertial sensors is presented. A new “hardware friendly” algorithm has been derived from the Rodrigues' rotation formula, which can be implemented in a more compact iterative structure. By exploiting 32-bit floating-point arithmetic, the design is able to combine high accuracy and low power requirements needed by any intelligent Human Activity Recognition system, based on artificial neural networks. Synthesis with 65 nm CMOS std _cells returns a power dissipation below 2 μ W and an area of about 0.05 mm2, Results are the current state-of-the-art for this kind of system and they are very promising for the future integration in smart sensors for wearable applications.

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Research paper thumbnail of Evaluation of NB-PLC in railway environments

2017 IEEE International Conference on Environment and Electrical Engineering and 2017 IEEE Industrial and Commercial Power Systems Europe (EEEIC / I&CPS Europe), 2017

In this paper, the possibility to use Narrow-Band Power-Line Communication (NB-PLC), based on PRI... more In this paper, the possibility to use Narrow-Band Power-Line Communication (NB-PLC), based on PRIME and G3-PLC protocols, in a particular harsh environment is demonstrated, with the purpose to significantly reduce the cable infrastructure and the related costs. To this end, the performances of a NB-PLC system have been measured when it is used in conjunction with an a.c. single phase power-line that delivers energy to the light signals in a railway environment. The context is very representative, since the lights in a terminal station and, hence, their controlling signals must obey to severe security standards and operate in a very harsh environment, populated by many electromagnetic interferences of several typologies, power sources and drain nodes. A testbed has been built, composed by the power generation core, the PLC modems and a cable long up to 2250m. Performance in terms of PSNR, RS SI, Throughput and BER have been reported for the entire modulation scheme that the PLC proto...

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Research paper thumbnail of Novel Advanced Analytical Design Tool for 4H-SiC VDMOSFET Devices

Materials Science Forum, 2017

An analytical tool to design 4H-SiC power vertical Double-diffused Metal-Oxide-Semiconductor Fiel... more An analytical tool to design 4H-SiC power vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect-Transistor is proposed. The model optimizes, in terms of the doping concentration in the Drift–region, the trade–off between the ON–resistance, RON, and the maximum blocking voltage, VBL, that is the Drain-Source voltage for which the avalanche breakdown appears at the p+–well/n-DRIFT junction together with the breakdown of the Gate oxide. Finding such trade-off means to maximize, Figure-Of-Merit. Our results are based on a novel full–analytical model of the electric field in the Gate oxide, EOX, whose generality is ensured by the absence of fitting and empirical parameters. Model results are successfully compared with 2D–simulations covering a wide range of device performances.

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Research paper thumbnail of Stream Processor for Real-Time Inverse Tone Mapping of Full-HD Images

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015

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Research paper thumbnail of Modeling of an Organic Thin Film Transistor as Temperature Sensor

Lecture notes in electrical engineering, Jun 29, 2022

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Research paper thumbnail of Quantized ID-CNN for a Low-power PDM-to-PCM Conversion in TinyML KWS Applications

2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS)

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Research paper thumbnail of Quantized Fully Convolution Neural Network for HW Implementation of Human Posture Recognition

2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS)

In this paper, a very tiny HW design of a Quantized Fully Convolutional Neural Network is propose... more In this paper, a very tiny HW design of a Quantized Fully Convolutional Neural Network is proposed which demonstrates that accurate Human Posture Recognition can be designed by exploiting only pressure sensors and keeping the computation close to the data sources, according to the edge computing paradigm. The custom design of the QFCN exploits a base-2 quantization scheme to achieve state-of-the-art performances in terms of classification accuracy, together with a very reduced number of mapped physical resources and power consumption. Trained and validated on a public dataset for in-bed posture classification, the QFCN exhibits an accuracy up to 96.77% in recognizing 17 different postures. When prototyped on a Xilinx Artix 7 FPGA the design achieves less than 7 mW dynamic power dissipation and a maximum operation frequency of 26.6 MHz, compatible with an Output Data Rate (ODR) of the sensors of 9.13 kHz.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Memory analysis of Interest Point Detector and Compact Descriptor algorithms

This document encloses analysis of portions of extraction module as composed by Difference of Gau... more This document encloses analysis of portions of extraction module as composed by Difference of Gaussian Interest Point Detector (DoG), Scale Invariant Feature Transform (SIFT) and Compressed Histogram of Gradients (ChoG) algorithms. With reference to TMuC, the Keypoint Selection, the Vector Quantization, and the Entropy Encoding were not considered in this analysis. The analysis, altought not fully completed, was mainly focused on the memory requirements and the feasibility of the system

Bookmarks Related papers MentionsView impact

Research paper thumbnail of A Model of the V-T Characteristics for an OTFT Temperature Sensor

2021 International Semiconductor Conference (CAS), 2021

An analytical model, able to describe the temperature dependence of the electrical characteristic... more An analytical model, able to describe the temperature dependence of the electrical characteristics of an organic thin film transistor (OTFT), is derived from the multiple trapping and release (MTR) theory related to an exponential distribution of tail states in the organic semiconductor layer at the insulator interface. The aim is to investigate the origin of the linearity of a temperature sensor based on a diode-connected OTFT, exhibiting a linearity of 99.93% and a sensitivity of about 110 mV/K, exceeding that of silicon-based sensors, when biased with a current of 16 nA. The model shows that the linear behavior is given by the compensation of two non-linear functions of temperature, one depending on the OTFT flat-band voltage, the other, varying with the bias current, on the interface state distribution.

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Research paper thumbnail of Feasibility of 4H-SiC p-i-n Diode for Sensitive Temperature Measurements Between 20.5 K and 802 K

IEEE Sensors Journal, 2019

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Multiplier-Less Stream Processor for 2D Filtering in Visual Search Applications

IEEE Transactions on Circuits and Systems for Video Technology, 2016

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Design of an offset-tolerant VSA bit-line sensing circuit for SRAM memories

Electronics Letters, 2016

The design of a new bit-line sensing scheme of SRAM memories is presented, which combines offset ... more The design of a new bit-line sensing scheme of SRAM memories is presented, which combines offset cancellation and compensation solutions. FCMOS inverters, brought to operate in their maximum gain region, are used to compensate the systematic offset of the sense amplifier and reduce the sensing delay. Systematic offset of the inverter amplifiers is cancelled by means of equalising feedback connections. A simulation analysis in Cadence environment and TSMC PDK demonstrates the very good potential of the proposed solution when it is compared with the recent and the established literature.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Physical model, measurement setup and experiments of a measurement technique of the carrier lifetime profile in power devices

2007 International Workshop on Physics of Semiconductor Devices, 2007

In this paper the physical model of a recently proposed technique to measure the spatial distribu... more In this paper the physical model of a recently proposed technique to measure the spatial distribution of the majority and minority carrier lifetime along silicon epilayers is presented. The model, verified by numerical simulations, clarifies the behaviour of the test structure used in the technique and gives a physical interpretation of the measured quantities. Experimental measurements are also presented, performed by using a measurement setup which ensures correct and noiseless results.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of A self-consistent model of the static and switching behaviour of 4H-SiC diodes

CAS 2010 Proceedings (International Semiconductor Conference), 2010

A novel model which is capable of describing with significant accuracy the temporal-spatial distr... more A novel model which is capable of describing with significant accuracy the temporal-spatial distributions of the minority carriers in 4H-SiC p-i-n diodes is presented. The analytical behaviour of the current, voltage and carrier distributions is compared with numerical simulations and with experimental results.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Experimental measurements of majority and minority carrier lifetime profile in SI epilayers by the use of an improved OCVD method

IEEE Electron Device Letters, 2005

In this letter, the first experimental results of a recently proposed technique for measuring the... more In this letter, the first experimental results of a recently proposed technique for measuring the carrier lifetime profile are presented. The technique makes use of a four-terminal bipolar test structure to electrically define the epilayer volume where recombination occurs and employs the open circuit voltage decay method for lifetime parameters extraction. For the capability of the test structure to depurate

Bookmarks Related papers MentionsView impact

Research paper thumbnail of CDVS: STM Detector Hw accelerator feasibility study and demonstrator

In order to validate feasibility of HW acceleration for interest point detection, one of the most... more In order to validate feasibility of HW acceleration for interest point detection, one of the most computational intensive part of the CDVS pipeline, STM has designed and implemented on FPGA a draft HW accelerator IP and demonstration is provided

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Low Power Tiny Binary Neural Network with improved accuracy in Human Recognition Systems

2020 23rd Euromicro Conference on Digital System Design (DSD)

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