Nabihah Ahmad | Universiti Tun Hussein Onn Malaysia (original) (raw)
Papers by Nabihah Ahmad
2021 6th IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE), 2021
The home automation system provides safety, living quality, and energy savings for the user. Its ... more The home automation system provides safety, living quality, and energy savings for the user. Its popularity is hampered by system complexity and power consumption, does not include a security system, and faced service disturbance during power outages. Thus, a small and compact automated home system controller which combines the comfort, security, and automated load transfer switch is proposed and designed under Application Specific Integrated Circuits (ASIC) design's flow. The Register Transfer Level (RTL) logic design and its testbench are developed at 100MHz for pre-and post-functional verification with ModelSim-Altera and Synopsys VCS. A 90nm TSMC technology is used for the area and power optimization in logical synthesis and physical synthesis via Synopsys Design Compiler and Synopsys IC Compiler. Implementation of the Pulse Width Modulation (PWM) methodology in the comfortable lighting system control increases the system's energy efficiency. 5ms of period pulses are successfully obtained for the duty cycle generation to prevent humans from perceiving light's blinking. The top-level module was able to function correctly based on the stimuli given by the input sensors. The final layout of the automated home system controller is effectively implemented with a total power consumption of 65.61 μW and a total area of 662.44μm2. The static and dynamic power dissipation is scaled down in physical synthesis stages by archiving 0.31μW and 4.67μW lower than logical synthesis. A significant reduction of cell area of the design with 17.75 μm2 was observed in the physical synthesis stage. The proposed design is advanced from the previous research and able to control home comfort, home security and automatically switch the stable powerline to load for power outages prevention.
As a snatch theft has become a serious problem to the society, it is required an immediate action... more As a snatch theft has become a serious problem to the society, it is required an immediate action to put an end to this problem. One of the solutions is to develop Smart Hand Bag system using Radio Frequency (RF) signal and location tracker as the main component. This project is implemented using an Arduino microcontroller, RF transmitter and receiver module, SIM900 Global System for Mobile Communications (GSM) and Global Positioning System (GPS) module, and 9dB buzzer. This smart handbag produces a loud sound to attract people surrounding whenever a snatch crime happens. The system is also able to track the location of the handbag by using GPS. The location tracked by the GPS module will be sent to the victim by using Short Messaging Service (SMS). Hence, this successfully developed Smart Hand Bag project is expected to help women to prevent this crime from spreading.
Low power consumption and high performance in Very Large Scale Integration (VLSI) design are the ... more Low power consumption and high performance in Very Large Scale Integration (VLSI) design are the major concerns in order to develop an efficient electronic devices. Addition is commonly used arithmetic operation in most electronic system which requires high performance and low power consumption of full adder circuit. This study aimed to design a low power and high performance full adder-subtractor by using Complementary Metal Oxide Semiconductor (CMOS) technology. Four design approaches of 4 bit Full Adder-Subtractor (FAS) static CMOS FAS with Pass Transistor Logic (PTL) XOR, static CMOS FAS with Transmission Gate (TG) XOR, PTL FAS and TG FAS circuit have been implemented in 90 nm CMOS technology using synopsys galaxy custom designer and compared in term of power consumption, power-delay product and area. PTL FAS able to reduce 27.7% of overall transistor count compared to both conventional static CMOS approach. For the 4 bit FAS design, PTL logic approach able to reduce 37.78% of a...
Concurrent fault detection plays a vital role in hardware implementation in order to prevent losi... more Concurrent fault detection plays a vital role in hardware implementation in order to prevent losing the original message This paper explores the new low-cost fault detection scheme for the S-box/ InvS-box of AES using a parity prediction technique. The predicted block was divided into seven blocks, to compare between the actual parity output and the predicted parity output results in the error indication flag for the corresponding block. The predicted blocks were developed with formulations compatible with the new S-box/ InvS-box simulated using 130nm CMOS technology, in Mentor Graphic environment. This proposed fault detection has achieved the total error coverage of about 99%. The total area implementation for the fault detection predicted parity block of the S-box/ InvS-box required 49 XORs, six XNORs, nine ANDs, one inverter, two ORs and one NAND gate. The proposed fault detection has the low hardware complexities which lead to a low cost and low power design.
Journal of Telecommunication, Electronic and Computer Engineering, 2017
Titanium Dioxide (TiO2) has been successfully prepared using the spray pyrolysis method. Then it ... more Titanium Dioxide (TiO2) has been successfully prepared using the spray pyrolysis method. Then it was optimized by conducting several repetition procedures and deposited on fluorine tin oxide (FTO) substrate. The amount of TiO2 P25 was varied from 0.1 grams (g) to 0.5 g in order to study the exact amount of TiO2 P25 needed to produce the highest efficiency solar cell result. All the thin films were annealed at fixed temperature at 500oC within 3 hours. The thickness of the thin film was measured through a surface profiler. From the measurement, it can be concluded that the utilization of different amount of TiO2 P25 affects the thickness of thin film. The properties of TiO 2 thin film were investigated by Field Emission Scanning Electron Microscopy (FE-SEM), X-ray Diffraction (XRD) and Four Point Probes. The amount of TiO2 P25 shows the notable effect on morphological and structural of deposit-TiO2. The optimum porosity of thin film was observed when 0.3g of TiO2 P25 has been used wh...
IOP Conference Series: Materials Science and Engineering, 2020
With the future technology and architecture, the digital musical instruments have been designed i... more With the future technology and architecture, the digital musical instruments have been designed into a pack of electronic hardware and software with no strings or animal skins for producing an instruments sound. One of the musical instruments with high interest to learn by a beginner is piano. To solve this problem, this research aimed to design and development of basic digital piano keyboard using FPGA for rapid prototyping. The core of this project is keynotes which is a common input peripheral device that is connected with FPGA which is DE1-SoC-MTL2 and speaker to complete a basic learning system of piano. The architecture is designed using Verilog HDL through the Altera Quartus Prime software. Verilog has been designed to export every 13 keys to 13 certain note then implemented on DE1-SoC-MTL2. The basic system process is a keynote press is needed to activate or produce the certain piano sound. MTL2 used to display a pressed keynote. There are 13 keys in total of piano keynotes ...
Journal of Telecommunication, Electronic and Computer Engineering, 2017
This work focuses on the analysis of structural, morphological, topological and optical propertie... more This work focuses on the analysis of structural, morphological, topological and optical properties of n-type cuprous oxide (Cu2O) thin film through the various duration of the annealing process. The n-type Cu2O thin film used in this research was fabricated on Fluorine-Doped Tin Oxide (FTO) glass substrate by using potentiostat electrodeposition method at optimized parameters. The optimized parameters were fixed at pH 6.3, temperature of 60oC, deposition time of 30 minutes and potential voltage at -0.125 V vs Ag/AgCl. Then, the samples of n-type Cu2O were subjected to a different annealing time set of 20, 30, 40, 50 and 60 minutes. It was found that the most optimized annealing duration was 60 minutes with a fixed annealing temperature of 200 oC. From the results, the properties of the n-type Cu2O thin film had enhanced by introduction of the annealing process. All the properties had characterized by using X-Ray Diffraction (XRD), Field Emission-Scanning Electron Microscopy (FE-SEM)...
Advanced Encryption Standard (AES) is a common symmetric encryption algorithm and widely implemen... more Advanced Encryption Standard (AES) is a common symmetric encryption algorithm and widely implemented in Wireless Local Area Network (WLAN), Radio Frequency Identification (RFID) tags and Bluetooth controller as the default choice for security services in its application. Substitution box (S-box) is a non-linear transformation and the core of AES implementation which consumed most of the power in AES hardware. This paper presents a low-complexity design methodology for the S-box/ Inverse S-box (Inv S-box) implemented in Field-Programmable Gate Array (FPGA) using composite field arithmetic and Quartus II as a tool to obtain simulation results through Verilog Hardware Description Language (HDL). This design utilized 94 slices with the hardware cost of the S-box/InvS-box is about 172 logic gates, with the power consumption of 31mW and the throughput is 1.6Gbps obtained through calculation. The design is suitable for the portable device application which requires data security with a low...
Microelectronics Journal, 2021
Journal of Physics: Conference Series, 2018
Indonesian Journal of Electrical Engineering and Computer Science, 2020
The continuous flourishing of boarding schools in Malaysia have prompted a need for the developme... more The continuous flourishing of boarding schools in Malaysia have prompted a need for the development of outing systems that can manage the outing activities of students whilst ensuring their safety and security. In this project, a smart outing and attendance system that accurately records the details of all students and their respective outing activities is proposed. The development of this system via the XAMPP platform allows the information regarding students’ outing activities to be saved in an online database, whereby it is closely monitored and managed by the school authorities. Students who attend authorized outing activities have to scan their student ID card at an RFID reader which is installed at the main entrance of the school compound, where the information regarding their departure and arrival time at the school will be transmitted via an Arduino controller to the database. At the same time, this system sends a notification in the form of a WhatsApp message to the phone n...
Journal of Physics: Conference Series, 2020
Digital to Analog Converter (DAC) is the essential block to convert an input digital signal into ... more Digital to Analog Converter (DAC) is the essential block to convert an input digital signal into analog signal. The switching technique is the important parameter that will affect the performance of DAC where to ensure the analog output signal can be obtained without any missing code. The capacitor DAC is most famous architecture used to design the DAC and it produce high power efficiency. But, the number of unit capacitors in DAC increase exponentially due to the increasing of resolution and a DAC block occupies a largest area among many internal blocks in Successive Approximation Register (SAR) Analog to Digital Converter (ADC). The DAC was designed for 14-bit SAr ADC using a hybrid Rc DAC architecture. The design of DAC has been carried out by using 0.18μm CMOS Silterra process Technology. The simulation results are done with 3.3V voltage supply and obtained DNL within -0.39 LSB to 0.238 LSB. It occupies an area of 0.614μm2.
Journal of Physics: Conference Series, 2020
A comparator plays a significant role in the developing of ADC. This comparator aims to get small... more A comparator plays a significant role in the developing of ADC. This comparator aims to get small offset value for high resolution. Several architectures present to optimize the offset voltage. The comparator designed for a 14-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). The main advantage of the implemented comparator of SAR ADC, which is the right choice for high resolution. This schematic design and layout simulation have implemented in Silterra C18G process 0.18um CMOS Technology by using Synopsys EDA Tools with transient and Monte Carlo. A double tail regenerative comparator is studied and investigated during this project. The simulation results complete with a 3.3V power supply. This comparator operates in 5MHz clock frequency with offset voltage for the latch is 32mV.
Journal of Physics: Conference Series, Jul 1, 2018
A tri-state charge pump circuit and second order low pass filter circuit were designed to be used... more A tri-state charge pump circuit and second order low pass filter circuit were designed to be used in Phase Lock Loop (PLL) system. The proposed design reduces the non-ideal effects such as a current mismatch and charge sharing. Therefore, it can be minimized by providing an equal value for the two switches UP and DOWN. While the charge pump output determines the output condition of the low pass filter. The proposed design have been simulated by using 130nm Complementary Metal Oxide Semiconductor (CMOS) technology in Cadence Tools. The simulation also includes the parameters for tri-state charge pump and second order low pass filter using voltage supply of 1.2 V. The power consumption of the design is 2.07 mW with the output voltage swing from 288 mV to 413.8 mV. The frequency achieved from the proposed design is 4.7 GHz. The total area of the layout that have been measured is 31.4 µm x 22.6 µm (0.7096 mm 2). Thus, the proposed design able to achieve the scope of low power consumption and high frequency in smaller technology.
Journal of Physics: Conference Series, 2018
This paper presents experimental results that compares between a full software (SW) implementatio... more This paper presents experimental results that compares between a full software (SW) implementation and a software/hardware (SW/HW) co-design implementation of a DSP algorithm on a Xilinx Zynq programmable System-on-chip (SoC). The case study being used is the 8x8 two-dimensional discrete cosine transform (2D DCT), present in the popular JPEG and MPEG4-AVC encoder. The full SW design is implemented on a hardcore ARM processor on the FPGA SoC. The SW/HW co-design utilizes both the ARM processor and the Configurable Logic Blocks (CLB) of the FPGA SoC, where the communication channel is implemented using the Xillybus FIFO buffers, implemented as an external DRAM. In this case, the core 2D DCT operations are executed on the CLB, while data initialization and transfers are implemented on the processor. Results show that SW implementation is faster compared to SW/HW implementation for data inputs of less than 0.48 megapixels. As data inputs get larger, SW/HW implementation shows better performance, with up to 2x faster for 2 megapixels data input size. This study proves the viability of implementing the 2D DCT operations as dedicated hardware accelerator in multimedia encoders.
Journal of Physics: Conference Series, 2018
View the article online for updates and enhancements. You may also like Microscopic description o... more View the article online for updates and enhancements. You may also like Microscopic description of quadrupoleoctupole coupling in actinides with the Gogny-D1M energy density functional R Rodríguez-Guzmán, Y M Humadi and L M Robledo-Bias patterns and climate change signals in GCM-RCM model chains Silje
ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING: FROM THEORY TO APPLICATIONS (SERIES 2): Proceedings of the International Conference of Electrical and Electronic Engineering (ICon3E 2019), 2019
This paper demonstrated a compact area of ultra-wideband (UWB) band pass filter (BPF) design usin... more This paper demonstrated a compact area of ultra-wideband (UWB) band pass filter (BPF) design using Hourglass filtering function in 5 th and 6 th order with 130nm CMOS technology. In this work, both proposed filters exhibits excellent performance such as low insertion loss (<1.69dB), greater return loss (>15dB), high selectivity, pass band width cover whole UWB spectrum (3.1-10.6GHz) and able to reject the wireless local area network (WLAN) interference signal. Zigzag technique is applied in both order filters to minimize the number of inductors and transmission zeros were added at the pass band edge for obtaining a perfect stopband rejection. The area achieved in these filter designs are 0.959mm x 0.812mm (0.779mm 2) and 1.153mm x 0.837mm (0.965mm 2) for 5 th and 6 th order respectively. As the proposed UWB BPF aim to be implemented in wireless application, this area is considered compact compared with relevant works.
Indonesian Journal of Electrical Engineering and Computer Science, 2019
In digital system, the full adders are fundamental circuits that are used for arithmetic operatio... more In digital system, the full adders are fundamental circuits that are used for arithmetic operations. Adder operation can be used to implement and perform calculation of the multipliers, subtraction, comparators, and address operation in an Arithmetic Logic Unit (ALU). The subthreshold leakage current increasing as proportional with the scaling down of oxide thickness and transistor in short channel sizes. In this paper, a Gate-diffusion Input (GDI) circuit design technique allow minimization the number of transistor while maintaining low complexity of logic design and low power realization of Variable Body Biasing (VBB) technique to reduce the static power consumption. The Silterra 90nm process design kit (PDK) was used to design 8-bit full adder with VBB technique in full custom methodology by using Synopsys Electronic Design Automation (EDA) tools. The simulation of 8-bit full adder was compared within a conventional bias technique and VBB technique with operating voltage of supp...
Indonesian Journal of Electrical Engineering and Computer Science, 2019
In this paper, the comparative study of symmetrical Operational Transconductance Amplifier (OTA) ... more In this paper, the comparative study of symmetrical Operational Transconductance Amplifier (OTA) performance between 180 nm, 130 nm and 90 nm CMOS technology have been done thoroughly to find the relationship between voltage supply and bias current with performance parameters (gain, power consumption and Common-Mode Rejection Ratio (CMRR)). The OTA which adopts symmetrical topology is designed carefully and simulated using Synopsys HSpice software and the results are carefully analyzed and compared. The symmetrical OTA designed in 90 nm CMOS technology is found to be the best because the power consumed is only 9.83 µW from ±0.9 V voltage supply and the OTA achieved 55.9 dB of the DC gain. The CMRR of the symmetrical 90 nm OTA is 140 dB which is sufficient to reject the common-mode signals in electrocardiogram (ECG) input signal. The symmetrical 90 nm OTA is suitable to be implemented as bioamplifier in ECG signal detection system as it consumed low power and has a high CMRR characte...
IOP Conference Series: Materials Science and Engineering, 2017
Multiplier is one of the essential component in the digital world such as in digital signal proce... more Multiplier is one of the essential component in the digital world such as in digital signal processing, microprocessor, quantum computing and widely used in arithmetic unit. Due to the complexity of the multiplier, tendency of errors are very high. This paper aimed to design a 2x2 bit Fault Tolerance Multiplier based on Reversible logic gate with low power consumption and high performance. This design have been implemented using 90nm Complemetary Metal Oxide Semiconductor (CMOS) technology in Synopsys Electronic Design Automation (EDA) Tools. Implementation of the multiplier architecture is by using the reversible logic gates. The fault tolerance multiplier used the combination of three reversible logic gate which are Double Feynman gate (F2G), New Fault Tolerance (NFT) gate and Islam Gate (IG) with the area of 160µm x 420.3µm (67.25 mm²). This design achieved a low power consumption of 122.85µW and propagation delay of 16.99ns. The fault tolerance multiplier proposed achieved a low power consumption and high performance which suitable for application of modern computing as it has a fault tolerance capabilities.
2021 6th IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE), 2021
The home automation system provides safety, living quality, and energy savings for the user. Its ... more The home automation system provides safety, living quality, and energy savings for the user. Its popularity is hampered by system complexity and power consumption, does not include a security system, and faced service disturbance during power outages. Thus, a small and compact automated home system controller which combines the comfort, security, and automated load transfer switch is proposed and designed under Application Specific Integrated Circuits (ASIC) design's flow. The Register Transfer Level (RTL) logic design and its testbench are developed at 100MHz for pre-and post-functional verification with ModelSim-Altera and Synopsys VCS. A 90nm TSMC technology is used for the area and power optimization in logical synthesis and physical synthesis via Synopsys Design Compiler and Synopsys IC Compiler. Implementation of the Pulse Width Modulation (PWM) methodology in the comfortable lighting system control increases the system's energy efficiency. 5ms of period pulses are successfully obtained for the duty cycle generation to prevent humans from perceiving light's blinking. The top-level module was able to function correctly based on the stimuli given by the input sensors. The final layout of the automated home system controller is effectively implemented with a total power consumption of 65.61 μW and a total area of 662.44μm2. The static and dynamic power dissipation is scaled down in physical synthesis stages by archiving 0.31μW and 4.67μW lower than logical synthesis. A significant reduction of cell area of the design with 17.75 μm2 was observed in the physical synthesis stage. The proposed design is advanced from the previous research and able to control home comfort, home security and automatically switch the stable powerline to load for power outages prevention.
As a snatch theft has become a serious problem to the society, it is required an immediate action... more As a snatch theft has become a serious problem to the society, it is required an immediate action to put an end to this problem. One of the solutions is to develop Smart Hand Bag system using Radio Frequency (RF) signal and location tracker as the main component. This project is implemented using an Arduino microcontroller, RF transmitter and receiver module, SIM900 Global System for Mobile Communications (GSM) and Global Positioning System (GPS) module, and 9dB buzzer. This smart handbag produces a loud sound to attract people surrounding whenever a snatch crime happens. The system is also able to track the location of the handbag by using GPS. The location tracked by the GPS module will be sent to the victim by using Short Messaging Service (SMS). Hence, this successfully developed Smart Hand Bag project is expected to help women to prevent this crime from spreading.
Low power consumption and high performance in Very Large Scale Integration (VLSI) design are the ... more Low power consumption and high performance in Very Large Scale Integration (VLSI) design are the major concerns in order to develop an efficient electronic devices. Addition is commonly used arithmetic operation in most electronic system which requires high performance and low power consumption of full adder circuit. This study aimed to design a low power and high performance full adder-subtractor by using Complementary Metal Oxide Semiconductor (CMOS) technology. Four design approaches of 4 bit Full Adder-Subtractor (FAS) static CMOS FAS with Pass Transistor Logic (PTL) XOR, static CMOS FAS with Transmission Gate (TG) XOR, PTL FAS and TG FAS circuit have been implemented in 90 nm CMOS technology using synopsys galaxy custom designer and compared in term of power consumption, power-delay product and area. PTL FAS able to reduce 27.7% of overall transistor count compared to both conventional static CMOS approach. For the 4 bit FAS design, PTL logic approach able to reduce 37.78% of a...
Concurrent fault detection plays a vital role in hardware implementation in order to prevent losi... more Concurrent fault detection plays a vital role in hardware implementation in order to prevent losing the original message This paper explores the new low-cost fault detection scheme for the S-box/ InvS-box of AES using a parity prediction technique. The predicted block was divided into seven blocks, to compare between the actual parity output and the predicted parity output results in the error indication flag for the corresponding block. The predicted blocks were developed with formulations compatible with the new S-box/ InvS-box simulated using 130nm CMOS technology, in Mentor Graphic environment. This proposed fault detection has achieved the total error coverage of about 99%. The total area implementation for the fault detection predicted parity block of the S-box/ InvS-box required 49 XORs, six XNORs, nine ANDs, one inverter, two ORs and one NAND gate. The proposed fault detection has the low hardware complexities which lead to a low cost and low power design.
Journal of Telecommunication, Electronic and Computer Engineering, 2017
Titanium Dioxide (TiO2) has been successfully prepared using the spray pyrolysis method. Then it ... more Titanium Dioxide (TiO2) has been successfully prepared using the spray pyrolysis method. Then it was optimized by conducting several repetition procedures and deposited on fluorine tin oxide (FTO) substrate. The amount of TiO2 P25 was varied from 0.1 grams (g) to 0.5 g in order to study the exact amount of TiO2 P25 needed to produce the highest efficiency solar cell result. All the thin films were annealed at fixed temperature at 500oC within 3 hours. The thickness of the thin film was measured through a surface profiler. From the measurement, it can be concluded that the utilization of different amount of TiO2 P25 affects the thickness of thin film. The properties of TiO 2 thin film were investigated by Field Emission Scanning Electron Microscopy (FE-SEM), X-ray Diffraction (XRD) and Four Point Probes. The amount of TiO2 P25 shows the notable effect on morphological and structural of deposit-TiO2. The optimum porosity of thin film was observed when 0.3g of TiO2 P25 has been used wh...
IOP Conference Series: Materials Science and Engineering, 2020
With the future technology and architecture, the digital musical instruments have been designed i... more With the future technology and architecture, the digital musical instruments have been designed into a pack of electronic hardware and software with no strings or animal skins for producing an instruments sound. One of the musical instruments with high interest to learn by a beginner is piano. To solve this problem, this research aimed to design and development of basic digital piano keyboard using FPGA for rapid prototyping. The core of this project is keynotes which is a common input peripheral device that is connected with FPGA which is DE1-SoC-MTL2 and speaker to complete a basic learning system of piano. The architecture is designed using Verilog HDL through the Altera Quartus Prime software. Verilog has been designed to export every 13 keys to 13 certain note then implemented on DE1-SoC-MTL2. The basic system process is a keynote press is needed to activate or produce the certain piano sound. MTL2 used to display a pressed keynote. There are 13 keys in total of piano keynotes ...
Journal of Telecommunication, Electronic and Computer Engineering, 2017
This work focuses on the analysis of structural, morphological, topological and optical propertie... more This work focuses on the analysis of structural, morphological, topological and optical properties of n-type cuprous oxide (Cu2O) thin film through the various duration of the annealing process. The n-type Cu2O thin film used in this research was fabricated on Fluorine-Doped Tin Oxide (FTO) glass substrate by using potentiostat electrodeposition method at optimized parameters. The optimized parameters were fixed at pH 6.3, temperature of 60oC, deposition time of 30 minutes and potential voltage at -0.125 V vs Ag/AgCl. Then, the samples of n-type Cu2O were subjected to a different annealing time set of 20, 30, 40, 50 and 60 minutes. It was found that the most optimized annealing duration was 60 minutes with a fixed annealing temperature of 200 oC. From the results, the properties of the n-type Cu2O thin film had enhanced by introduction of the annealing process. All the properties had characterized by using X-Ray Diffraction (XRD), Field Emission-Scanning Electron Microscopy (FE-SEM)...
Advanced Encryption Standard (AES) is a common symmetric encryption algorithm and widely implemen... more Advanced Encryption Standard (AES) is a common symmetric encryption algorithm and widely implemented in Wireless Local Area Network (WLAN), Radio Frequency Identification (RFID) tags and Bluetooth controller as the default choice for security services in its application. Substitution box (S-box) is a non-linear transformation and the core of AES implementation which consumed most of the power in AES hardware. This paper presents a low-complexity design methodology for the S-box/ Inverse S-box (Inv S-box) implemented in Field-Programmable Gate Array (FPGA) using composite field arithmetic and Quartus II as a tool to obtain simulation results through Verilog Hardware Description Language (HDL). This design utilized 94 slices with the hardware cost of the S-box/InvS-box is about 172 logic gates, with the power consumption of 31mW and the throughput is 1.6Gbps obtained through calculation. The design is suitable for the portable device application which requires data security with a low...
Microelectronics Journal, 2021
Journal of Physics: Conference Series, 2018
Indonesian Journal of Electrical Engineering and Computer Science, 2020
The continuous flourishing of boarding schools in Malaysia have prompted a need for the developme... more The continuous flourishing of boarding schools in Malaysia have prompted a need for the development of outing systems that can manage the outing activities of students whilst ensuring their safety and security. In this project, a smart outing and attendance system that accurately records the details of all students and their respective outing activities is proposed. The development of this system via the XAMPP platform allows the information regarding students’ outing activities to be saved in an online database, whereby it is closely monitored and managed by the school authorities. Students who attend authorized outing activities have to scan their student ID card at an RFID reader which is installed at the main entrance of the school compound, where the information regarding their departure and arrival time at the school will be transmitted via an Arduino controller to the database. At the same time, this system sends a notification in the form of a WhatsApp message to the phone n...
Journal of Physics: Conference Series, 2020
Digital to Analog Converter (DAC) is the essential block to convert an input digital signal into ... more Digital to Analog Converter (DAC) is the essential block to convert an input digital signal into analog signal. The switching technique is the important parameter that will affect the performance of DAC where to ensure the analog output signal can be obtained without any missing code. The capacitor DAC is most famous architecture used to design the DAC and it produce high power efficiency. But, the number of unit capacitors in DAC increase exponentially due to the increasing of resolution and a DAC block occupies a largest area among many internal blocks in Successive Approximation Register (SAR) Analog to Digital Converter (ADC). The DAC was designed for 14-bit SAr ADC using a hybrid Rc DAC architecture. The design of DAC has been carried out by using 0.18μm CMOS Silterra process Technology. The simulation results are done with 3.3V voltage supply and obtained DNL within -0.39 LSB to 0.238 LSB. It occupies an area of 0.614μm2.
Journal of Physics: Conference Series, 2020
A comparator plays a significant role in the developing of ADC. This comparator aims to get small... more A comparator plays a significant role in the developing of ADC. This comparator aims to get small offset value for high resolution. Several architectures present to optimize the offset voltage. The comparator designed for a 14-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). The main advantage of the implemented comparator of SAR ADC, which is the right choice for high resolution. This schematic design and layout simulation have implemented in Silterra C18G process 0.18um CMOS Technology by using Synopsys EDA Tools with transient and Monte Carlo. A double tail regenerative comparator is studied and investigated during this project. The simulation results complete with a 3.3V power supply. This comparator operates in 5MHz clock frequency with offset voltage for the latch is 32mV.
Journal of Physics: Conference Series, Jul 1, 2018
A tri-state charge pump circuit and second order low pass filter circuit were designed to be used... more A tri-state charge pump circuit and second order low pass filter circuit were designed to be used in Phase Lock Loop (PLL) system. The proposed design reduces the non-ideal effects such as a current mismatch and charge sharing. Therefore, it can be minimized by providing an equal value for the two switches UP and DOWN. While the charge pump output determines the output condition of the low pass filter. The proposed design have been simulated by using 130nm Complementary Metal Oxide Semiconductor (CMOS) technology in Cadence Tools. The simulation also includes the parameters for tri-state charge pump and second order low pass filter using voltage supply of 1.2 V. The power consumption of the design is 2.07 mW with the output voltage swing from 288 mV to 413.8 mV. The frequency achieved from the proposed design is 4.7 GHz. The total area of the layout that have been measured is 31.4 µm x 22.6 µm (0.7096 mm 2). Thus, the proposed design able to achieve the scope of low power consumption and high frequency in smaller technology.
Journal of Physics: Conference Series, 2018
This paper presents experimental results that compares between a full software (SW) implementatio... more This paper presents experimental results that compares between a full software (SW) implementation and a software/hardware (SW/HW) co-design implementation of a DSP algorithm on a Xilinx Zynq programmable System-on-chip (SoC). The case study being used is the 8x8 two-dimensional discrete cosine transform (2D DCT), present in the popular JPEG and MPEG4-AVC encoder. The full SW design is implemented on a hardcore ARM processor on the FPGA SoC. The SW/HW co-design utilizes both the ARM processor and the Configurable Logic Blocks (CLB) of the FPGA SoC, where the communication channel is implemented using the Xillybus FIFO buffers, implemented as an external DRAM. In this case, the core 2D DCT operations are executed on the CLB, while data initialization and transfers are implemented on the processor. Results show that SW implementation is faster compared to SW/HW implementation for data inputs of less than 0.48 megapixels. As data inputs get larger, SW/HW implementation shows better performance, with up to 2x faster for 2 megapixels data input size. This study proves the viability of implementing the 2D DCT operations as dedicated hardware accelerator in multimedia encoders.
Journal of Physics: Conference Series, 2018
View the article online for updates and enhancements. You may also like Microscopic description o... more View the article online for updates and enhancements. You may also like Microscopic description of quadrupoleoctupole coupling in actinides with the Gogny-D1M energy density functional R Rodríguez-Guzmán, Y M Humadi and L M Robledo-Bias patterns and climate change signals in GCM-RCM model chains Silje
ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING: FROM THEORY TO APPLICATIONS (SERIES 2): Proceedings of the International Conference of Electrical and Electronic Engineering (ICon3E 2019), 2019
This paper demonstrated a compact area of ultra-wideband (UWB) band pass filter (BPF) design usin... more This paper demonstrated a compact area of ultra-wideband (UWB) band pass filter (BPF) design using Hourglass filtering function in 5 th and 6 th order with 130nm CMOS technology. In this work, both proposed filters exhibits excellent performance such as low insertion loss (<1.69dB), greater return loss (>15dB), high selectivity, pass band width cover whole UWB spectrum (3.1-10.6GHz) and able to reject the wireless local area network (WLAN) interference signal. Zigzag technique is applied in both order filters to minimize the number of inductors and transmission zeros were added at the pass band edge for obtaining a perfect stopband rejection. The area achieved in these filter designs are 0.959mm x 0.812mm (0.779mm 2) and 1.153mm x 0.837mm (0.965mm 2) for 5 th and 6 th order respectively. As the proposed UWB BPF aim to be implemented in wireless application, this area is considered compact compared with relevant works.
Indonesian Journal of Electrical Engineering and Computer Science, 2019
In digital system, the full adders are fundamental circuits that are used for arithmetic operatio... more In digital system, the full adders are fundamental circuits that are used for arithmetic operations. Adder operation can be used to implement and perform calculation of the multipliers, subtraction, comparators, and address operation in an Arithmetic Logic Unit (ALU). The subthreshold leakage current increasing as proportional with the scaling down of oxide thickness and transistor in short channel sizes. In this paper, a Gate-diffusion Input (GDI) circuit design technique allow minimization the number of transistor while maintaining low complexity of logic design and low power realization of Variable Body Biasing (VBB) technique to reduce the static power consumption. The Silterra 90nm process design kit (PDK) was used to design 8-bit full adder with VBB technique in full custom methodology by using Synopsys Electronic Design Automation (EDA) tools. The simulation of 8-bit full adder was compared within a conventional bias technique and VBB technique with operating voltage of supp...
Indonesian Journal of Electrical Engineering and Computer Science, 2019
In this paper, the comparative study of symmetrical Operational Transconductance Amplifier (OTA) ... more In this paper, the comparative study of symmetrical Operational Transconductance Amplifier (OTA) performance between 180 nm, 130 nm and 90 nm CMOS technology have been done thoroughly to find the relationship between voltage supply and bias current with performance parameters (gain, power consumption and Common-Mode Rejection Ratio (CMRR)). The OTA which adopts symmetrical topology is designed carefully and simulated using Synopsys HSpice software and the results are carefully analyzed and compared. The symmetrical OTA designed in 90 nm CMOS technology is found to be the best because the power consumed is only 9.83 µW from ±0.9 V voltage supply and the OTA achieved 55.9 dB of the DC gain. The CMRR of the symmetrical 90 nm OTA is 140 dB which is sufficient to reject the common-mode signals in electrocardiogram (ECG) input signal. The symmetrical 90 nm OTA is suitable to be implemented as bioamplifier in ECG signal detection system as it consumed low power and has a high CMRR characte...
IOP Conference Series: Materials Science and Engineering, 2017
Multiplier is one of the essential component in the digital world such as in digital signal proce... more Multiplier is one of the essential component in the digital world such as in digital signal processing, microprocessor, quantum computing and widely used in arithmetic unit. Due to the complexity of the multiplier, tendency of errors are very high. This paper aimed to design a 2x2 bit Fault Tolerance Multiplier based on Reversible logic gate with low power consumption and high performance. This design have been implemented using 90nm Complemetary Metal Oxide Semiconductor (CMOS) technology in Synopsys Electronic Design Automation (EDA) Tools. Implementation of the multiplier architecture is by using the reversible logic gates. The fault tolerance multiplier used the combination of three reversible logic gate which are Double Feynman gate (F2G), New Fault Tolerance (NFT) gate and Islam Gate (IG) with the area of 160µm x 420.3µm (67.25 mm²). This design achieved a low power consumption of 122.85µW and propagation delay of 16.99ns. The fault tolerance multiplier proposed achieved a low power consumption and high performance which suitable for application of modern computing as it has a fault tolerance capabilities.