Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique (original) (raw)

System identification -based reduced-code testing for pipeline ADCs’ linearity test

2008 IEEE International Symposium on Circuits and Systems, 2008

This work presents a system identification-based reduced-code testing method for pipeline ADC's linearity test. In the method, the pipeline ADC under test is identified by characterizing the two most critical parameters in each stage, the stage gain and the comparator offset. The transfer function is investigated to obtain the effects of the gain error and comparator offset on ADC's linearity performance. With the measurements of a small set of specific transition levels or code bin widths, the system parameters of interest can be achieved using only straightforward linear calculations. The identified model is then used to compute the ADC's full-code linearity performance. Comparing to standard histogram-based full-code linearity test methods, the proposed method can reduce the data capture time by a factor of several hundreds without appreciably degrading the testing accuracy. Both simulation results and experimental results are included to demonstrate the efficacy of the proposed method.

Pipeline ADC Linearity Testing with Dramatically Reduced Data Capture Time

2005 IEEE International Symposium on Circuits and Systems

A system identification based method for testing pipeline ADC's linearity is presented. In the method, the pipeline ADC is described by an identifier model consisting of a set of nonlinear equations parameterized with some unknown parameters. A small number of input output response data points of the ADC is then used to identify those unknown parameters. The identified model is then used to compute the ADC's full-code linearity information. Comparing to standard histogram based fullcode linearity test methods, the proposed method can reduce the data capture time by a factor of 100 to 1000 without appreciably degrading the testing accuracy. Both simulation results and experimental results are included which demonstrate the efficacy of the proposed method.

A fully digital-compatible BIST strategy for ADC linearity testing

2007 IEEE International Test Conference, 2007

Digital testing is much easier and cheaper than analog and mixed-signal testing because of the straightforward connections and the low-cost testers. This paper presents a fully digital-compatible built-in self-test strategy for ADC linearity testing using all digital testing environments. Onchip, low-accuracy DACs, which are area efficient and simple to design, are implemented as the stimulus generator. ADCs' nonlinearities are tested using a histogram-based method under the control of a logic block. The described strategy is capable of characterizing ADC transition levels one by one with small hardware overhead. Simulation and experimental results show that the proposed circuitry and BIST strategy can test the INL k error of 12-bit ADCs to ±0.2LSB accuracy level using only 7-bit linear DACs.

High-Resolution ADC Linearity Testing Using a Fully Digital-Compatible BIST Strategy

IEEE Transactions on Instrumentation and Measurement, 2009

This paper proposes a digital-compatible built-in self-test (BIST) strategy for high-resolution analog-to-digital converter (ADC) linearity testing using only digital testing environments. The on-chip stimulus generator consists of three lowresolution and low-accuracy current steering digital-to-analog converters (DACs), which are area efficient and easy to design. The linearity of the stimuli is improved by the proposed reconfiguration technique. ADCs' outputs are evaluated by simple digital logic circuits to characterize the nonlinearities. The proposed BIST strategy is capable of characterizing ADC transition levels one by one with small hardware overhead. The testing performance is not sensitive to the mismatches and process variations, so that the analog BIST circuits can easily be reused without complex self-calibration. Simulation and experimental results show that the proposed circuitry and BIST strategy can test the INL k error of 12-bit ADCs to a ±0.15 least significant bit (LSB) accuracy level using only 7-bit linear DACs.

A new methodology for adc test flow optimization

International Test Conference, 2003. Proceedings. ITC 2003., 2003

Testing of Analog-to-Digital Converters is classically composed of two successive and independent phases: the histogram-based test technique evaluating static specifications and the spectral analysis technique evaluating the dynamic performances. Consequently, the fundamental objective here is to investigate the feasibility of an alternative test flow involving exclusively spectral analysis to replace these two time consuming and expensive phases. The viability of this solution depends on the ability of spectral analysis to detect static specifications. In this context, this paper presents a new methodology based on a statistical approach to quantitatively evaluate the efficiency of detecting static errors from dynamic parameter measurements. This methodology has been implemented in an in-house automatic tool allowing one to process any ADC specifications. It is then possible to choose a priori the best test flow for a given application considering the most adequate trade-off between test time and test efficiency.

D2. Testing of 1.5 Bit per Stage Pipelined Analog to Digital Converter: 5 Bits Case Study

2013 30th National Radio Science Conference (NRSC), 2013

Nowadays, Analog to Digital converters are the main building blocks of mixed analog/digital signal circuits, hence testing ADC circuits has become mandatory. The pipelined Analog-to-Digital Converter (PADC) is widely used with its famous 1.5 bit/stage architecture. In this paper, a low-cost test is developed for a 5 bit PADC. The 5 bits PADC consists of 3-stage (1.5 bit/stage) PADC followed by a 2 bit flash ADC. Then, the digital output of the 4-stage PADC is followed by its time alignment and Digital Error Correction (DEC) circuits. They are based on a 90 nm CMOS technology. It is proved that only six DC test values can detect 96.3% of catastrophic faults in the fault set. An extra analog pin is required in order to achieve 100% fault coverage. The Eldo simulator provided by Mentor Graphics was used in the analysis.

Reduced-Code Techniques for On-Chip Static Linearity Test of SAR ADCs

2019

This work presents reduced-code strategies for the static linearity test of successive-approximation analog-to-digital converters. Reduced-code techniques for ADC static linearity test may drastically reduce the test time for static linearity characterization. These techniques take advantage of the repetitive operation of SAR ADCs for reducing the number of necessary measurements for static linearity testing. In this paper we discuss the implementation of these techniques for three widely used SAR ADC topologies. Namely, we consider SAR ADCs based on binary-weighted capacitive DACs, split-capacitor DACs and segmented DACs. The proposed techniques are validated by behavioral simulations on three SAR ADC case studies.

Effective Adc Linearity Testing

2004

This paper deals with the effectiveness of the Sinewave Histogram Test (SHT) for testing analog to Digital Converters (ADCs). The implementation is discussed, with respect to the adopted procedures and to the choice of relevant parameters. Some of the published approximations currently limiting the characterization of the test performance are removed. Furthermore the statistical efficiency of the SHT is evaluated by comparing the associated estimator variance with the corresponding Cramér-Rao Lower Bound (CRLB), theoretically derived assuming sinewaves corrupted by Gaussian noise. Finally, both simulation and experimental results are presented to validate the proposed approach.