Ternary Logic Gates: Advancing Computing with -1, 0, 1 Base (original) (raw)

Imaginary Numbers in Logic Gates: Beyond Ternary Paradigms

2024

Background: Ternary logic gates, utilizing the base-1, 0, 1, represent a departure from conventional binary systems, offering expanded states for digital representation. This paper explores the integration of the imaginary unit i within ternary logic, introducing new dimensions to computing paradigms beyond traditional binary logic gates. Objectives: Our study aims to demonstrate the versatility and universality of NAND gates within ternary logic, utilizing the states-1, 0, 1, and investigating the implications of i in enhancing logic operations and system functionalities. Methods: Employing logical analysis and mathematical modeling, we design and implement NAND gates in a ternary logic framework to showcase their ability to construct diverse logic gates effectively. Results: Theoretical derivations and simulations illustrate the robustness of NAND gates in constructing various ternary logic gates, underscoring their functional completeness and computational efficiency. Conclusions: By integrating NAND gates with the imaginary unit i, this research not only replicates traditional binary logic functionalities but also explores novel applications in digital systems. The interpretations of i within ternary logic, such as symbolizing extreme cold or reactive states akin to dry ice, or representing oscillatory characteristics similar to AC currents, broaden the theoretical and practical understanding of ternary logic systems. This study contributes to advancing electronic circuit design and computation by exploring these new dimensions of signal representation and processing.

A proposal for the implementation of ternary digital circuits

Microelectronics Journal, 1997

A nonclassical multi-valued logic based on Post algebra is presented. Besides the conventional Post's cyclic negation, this nonclassical logic algebra defines new operators that simplify the truth-table minimization techniques. An electronic implementation of this algebra for a 3-level logic is proposed. Electronics gates of Post negation and the new operators were designed and simulated using current mode circuits. These gates can be easily interconnected to form flip-flops, counters and other conventional digital gates in a true 3-level gate logic. ASICs with mixed analog/digital high-speed processing can benefit from this current processing ternary logic, which can be easily implemented in bipolar technology.

Physical Design Implementation of Ternary Arithmetic Circuits

International Journal for Research in Applied Science and Engineering Technology, 2017

Trivalent logic is also called as ternary logic is a promising alternative to the conventional Boolean space. In modern VLSI, CMOS technologies are invented and the die size is reducing day by day. So the complexities on the die increases resulting into the high integration on the same die size. I order to drive the logic, we have to think about the multi-valued logic cell as there are some limitations with the conventional Boolean space. Ternary logic provides simplicity and energy efficiency in digital design as the logic reduces the complexity of interconnects and chip area along with the higher density of information storage. The proposed paper presents the physical design implementation of the various ternary arithmetic circuits which involves the universal gates as T-NAND and T-NOR. The ternary arithmetic based design are aimed to achieve the low power consumption, high stability. The physical designs are implemented and simulated using the Microwind 3.5 EDA tool with CMOS 45nm technology.

Ternary logic in digital system for high speed, performance and reduction of arithmetic circuitry

In this paper “Digital Transceiver using Advance Ternary Technique” gives the details about digital transmitter and receiver with the design of a ternary line coding. In this scheme computer data (byte) will be converted into base-3 data elements. Current applications of line codes are enormous in data transmission networks and in recording and storage of information systems. The applications include local and wide area networks both wireless and wire connected. A coding technique named advanced ternary line code can be derived from three popular line codes NRZ-L, NRZ and polar RZ. In this scheme six signal patterns are required for eight binary data patterns. 6 ternary arithmetic operations describe in this paper which reduce the cost of circuitry in compare to Binary computation circuitry

Implementation of Ternary Circuits with-Binary Integrated Circuits

IEEE Transactions on Computers, 1977

A general method for implementing ternary circuits with binary integrated circuits is described. The conditions are given for a particular technology to be able to implement ternary circuits. For TTL, COSMOS, and ECL technologies, the necessary circuits are developed. Formulas are provided to obtain the minimum circuit according to the particular function required. Simplification rules corresponding to each technology are given. Some examples illustrate the method. Some dynamical characteristics are shown. Extensions of these results to other technologies and to n-valued circuits are possible. Index Terms-Circuit realization of multivalued functions, combinational circuits, COSMOS integrated circuits, ECL integrated circuits, fundamental ternary circuits, multivalued circuits, ternary logic implementation, TTL integrated circuits.

Optimization of 1-Bit ALU using Ternary Logic

In this paper, we presented a novel approach for implementation of 1-bit ALU using Ternary logic. The ternary logic or Three Valued Logic (3VL) is the next alternative approach offering several advantages over existing conventional binary digital logic. The proposed 3VL based ALU is designed for 1-bit operation and can be used for real time applications with better hardware reduction in turn minimizing the number of gates over binary logic. The 3VL based ALU is designed using CMOS ternary logic gates (T-Gates) for ternary based arithmetic and logical circuits which is suitable for LSI/VLSI implementation. The design can be extended to n-bit operation for real time applications. Today's existing simulation tools do not permit the simulation of 3VL circuits. VHDL is used as a simulation tool for 3VL verification. An objective of this study is to describe how existing 3VL system can be optimized in terms of transistors over binary logic. Ternary logic resulted in 25% reduction of transistor utility in 1-Bit ALU design when compared to binary logic.

Realization of regular ternary logic functions using double-rail logic

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198), 1999

In logic simulation, we often have t o ev aluate logic functions in the presence of unknown inputs. However, the naive method often produces incorrect values. In these cases, we can produce correct values by evaluating regular ternary logic functions instead of switching functions. This paper proposes a realization of regular ternary logic functions by using double-rail logic. This implementation requires O(2 n =n) logic cells, and O(n) time to simulate an nvariable logic function. We showed an FPGA realization that is about 100 times faster than software simulation.

Realization of Ternary Reversible Circuits Using Improved Gate Library

Procedia Computer Science, 2016

Ternary logic has some distinct advantage over binary logic. In this paper we propose a synthesis approach for ternary reversible circuits using ternary reversible gates. Our method takes a boolean function as input. The input is provided as .pla file. The .pla file is first converted into ternary logic function, which can be represented as permutation. The gate library used for synthesis is Ternary Not, Ternary Toffoli and Ternary Toffoli + (N T ,T T ,T T +). The proposed constructive method, generates 3-cycles from the permutation, and then each 3-cycle is mapped to (N T ,T T ,T T +) gate library. Experimental results show that the method generates lesser number of gates for some circuits compared to previously reported works.

Arithmetic Logic Design with ColorCoded Ternary for Ternary Computing

International Journal, 2011

This paper introduces a novel means of representing ternary states using color-codes, suggests a logic design model for a ternary half adder circuit and separate carry circuits. A ternary simulator was also developed to aid in the research and development of ternary systems.

A Novel Mifgmos Transistor Based Approach for the Realization of Ternary Gates

ICTACT Journal on Microelectronics, 2015

Multi Valued Logic [MVL] has experienced major evolution in the recent past due to several advantages offered by them over the binary logic. Ternary Logic (a logic with radix 3 i.e. 3 logic states) is a promising alternative to the binary logic making it a thrust area of research. With the recent technological advancements, commercial realization of ternary circuits is watched with keen interests thereby attracting the attention of wide community of researchers to explore the usability of various alternative devices for implementing ternary circuits. This research proposes a novel hybrid approach based on combination of MIFGMOS (Multi Input Floating Gate Metal Oxide Semiconductor) transistor and conventional MOSFET for the realization of the ternary gates. In a digital system, NOT, NAND and NOR are of more importance as they are the building blocks of many other complex logic and arithmetic circuits. In this paper, the designs (based on hybrid combination of devices) of two input TNAND and TNOR gates are detailed which along with MIFGMOS transistor based T-inverter are further used to design TAND, TOR, TXOR and TXNOR gates. An extensive simulation of all the designed gates is carried out using TSPICE circuit simulator. The results demonstrate expected functionality of the proposed hybrid gates and additionally signify improvement in the performance parameters. The proposed hybrid approach combines the virtues of both the devices which facilitate the significant reduction in the circuit element count of the ternary gates as compared to earlier reported methods.