Optimization of 1-Bit ALU using Ternary Logic (original) (raw)

Physical Design Implementation of Ternary Arithmetic Circuits

International Journal for Research in Applied Science and Engineering Technology, 2017

Trivalent logic is also called as ternary logic is a promising alternative to the conventional Boolean space. In modern VLSI, CMOS technologies are invented and the die size is reducing day by day. So the complexities on the die increases resulting into the high integration on the same die size. I order to drive the logic, we have to think about the multi-valued logic cell as there are some limitations with the conventional Boolean space. Ternary logic provides simplicity and energy efficiency in digital design as the logic reduces the complexity of interconnects and chip area along with the higher density of information storage. The proposed paper presents the physical design implementation of the various ternary arithmetic circuits which involves the universal gates as T-NAND and T-NOR. The ternary arithmetic based design are aimed to achieve the low power consumption, high stability. The physical designs are implemented and simulated using the Microwind 3.5 EDA tool with CMOS 45nm technology.

A proposal for the implementation of ternary digital circuits

Microelectronics Journal, 1997

A nonclassical multi-valued logic based on Post algebra is presented. Besides the conventional Post's cyclic negation, this nonclassical logic algebra defines new operators that simplify the truth-table minimization techniques. An electronic implementation of this algebra for a 3-level logic is proposed. Electronics gates of Post negation and the new operators were designed and simulated using current mode circuits. These gates can be easily interconnected to form flip-flops, counters and other conventional digital gates in a true 3-level gate logic. ASICs with mixed analog/digital high-speed processing can benefit from this current processing ternary logic, which can be easily implemented in bipolar technology.

Implementation of Ternary Circuits with-Binary Integrated Circuits

IEEE Transactions on Computers, 1977

A general method for implementing ternary circuits with binary integrated circuits is described. The conditions are given for a particular technology to be able to implement ternary circuits. For TTL, COSMOS, and ECL technologies, the necessary circuits are developed. Formulas are provided to obtain the minimum circuit according to the particular function required. Simplification rules corresponding to each technology are given. Some examples illustrate the method. Some dynamical characteristics are shown. Extensions of these results to other technologies and to n-valued circuits are possible. Index Terms-Circuit realization of multivalued functions, combinational circuits, COSMOS integrated circuits, ECL integrated circuits, fundamental ternary circuits, multivalued circuits, ternary logic implementation, TTL integrated circuits.

Design And Implementation Of 2 Bit Ternary ALU Slice

This paper describes the architecture, design & implementation of 2 bit ternary ALU (T-ALU) slice. The proposed ALU is designed for two-bit operation & can be used for n bit operations by cascading n/2 ALU slices. This ALU is implemented using C-MOS ternary logic gates (T-Gates) for ternary arithmetic & logic circuits. Ternary gates are implemented using enhancement / depletion MOSFET technology, thus proposed ALU is suitable for LSI / VLSI implementation. The designed technique used here requires only two stages i.e. decoder & T-gates, as against three stages i.e. decoder, binary gates & encoder require in conventional ternary logic implementation.

Design of Low Power Low Voltage Circuit using CMOS Ternary Logic

— Binary logic and devices have been in use since inception with advancement and technology and millennium gate design era. Now binary logic has become tedious and complicated. For this purpose the low power and low voltage arithmetic and logic circuit designed. In this paper we will presents the design and performance of Arithmetic and Logic circuit using Ternary logic and CMOS design styles. The design is targeted for the 45nm CMOS technology. Design tool for simulation will be MICROWIND 3.1 software and DSCH tool. We will estimate area, power and delay and the design of arithmetic circuit with optimized number of transistors as compared to binary circuit.

Ternary logic in digital system for high speed, performance and reduction of arithmetic circuitry

In this paper “Digital Transceiver using Advance Ternary Technique” gives the details about digital transmitter and receiver with the design of a ternary line coding. In this scheme computer data (byte) will be converted into base-3 data elements. Current applications of line codes are enormous in data transmission networks and in recording and storage of information systems. The applications include local and wide area networks both wireless and wire connected. A coding technique named advanced ternary line code can be derived from three popular line codes NRZ-L, NRZ and polar RZ. In this scheme six signal patterns are required for eight binary data patterns. 6 ternary arithmetic operations describe in this paper which reduce the cost of circuitry in compare to Binary computation circuitry

Modeling and Implementation of Reliable Ternary Arithmetic and Logic Unit Design Using Vhdl

Multivalve logic is a reliable method for defining, analyzing, testing and implementing the basic combinational circuitry with VHDL simulator. It offers better utilization of transmission channels because of its high speed for higher information carried out and it gives more efficient performance. One of the main realizing of the MVL (ternary logic) is that reduces the number of required computation steps, simplicity and energy efficiency in digital logic design. This paper using reliable method is brought out for implementing the basic combinational, sequential and TALU (Ternary Arithmetic and Logic Unit) circuitry with minimum number of ternary switching circuits (Multiplexers). In this the potential of VHDL modelling and simulation that can be applied to ternary switching circuits to verify its functionality and timing specifications. An intention is to show how proposed simulator can be used to simulate MVL circuits and to evaluate system performance.

Design and characterization of a low power ternary DSP

2003

ABSTRACT This paper deals with design and performance estimation of typical units blocks of a ternary DSP using SUS-LOC concepts. SUS-LOC enables the design of ternary logic cells and is based upon the use of enhanced and depleted MOS transistors. After the presentation of the basic concepts and of the transistor models required for SUS-LOC specific transistors, we show the design of ternary combinatorial and sequential cells. VHDL is used to obtain performances modelling and architectural-level simulation.

Multiple-Valued Logic Circuit Design and Data Transmission Intended for Embedded Systems

Cornell University - arXiv, 2022

Recently, the demand for portable electronics and embedded systems has increased. These devices need low-power circuit designs because they depend on batteries as an energy resource. Moreover, Multi-Valued Logic (MVL) circuits provide notable improvements over binary circuits in terms of interconnect complexity, chip area, propagation delay, and energy consumption. Therefore, this thesis proposes novel ternary circuits aiming to reduce the energy (Power Delay Product (PDP)) to preserve battery consumption. The proposed designs include eight ternary logic gates, three ternary combinational circuits, and six Ternary Arithmetic Logic Units (TALU). The ternary logic gates are seven unary operators of the ternary system (A 1 , A 2 ,Ā 2 , A 1 , 1.Ā n , 1.Ā p , and the Standard Ternary Inverter (STI)Ā), and Ternary NAND based on Carbon Nanotube Field-Effect Transistor (CNFET). Ternary combinational circuits, two different designs for Ternary Decoders (TDecoder) and Ternary Multiplexer (TMUX): (1) TDecoder1 using CNFET-based proposed unary operators and TDecoder2 using Double-Pass Logic (DPL) binary gates. (2) TMUX using CNFET-based proposed unary operators. And Ternary Arithmetic Logic Units are three different designs for Ternary Half-Adders (THA) and Ternary Multipliers (TMUL): (1) The first design uses the proposed TDecoder1, STI, and TNAND. (2) While the second design uses the cascading proposed TMUX. (3) As for the third design, it uses the proposed unary operators and TMUX. This thesis applies the best trade-off between reducing the number of used transistors, utilizing energy-efficient transistor arrangement such as transmission gate and applying the dual supply voltages (Vdd, and Vdd/2) to achieve its objective. The proposed designs are compared to the latest ternary circuits using the HSPICE simulator for different supply voltages, different temperatures, and different frequencies. Simulations are performed to prove the efficiency of the proposed designs. The results demonstrate the advantage of the proposed designs with a reduction over 73% in terms of transistors count for the THA and over 88%, v 99%, 98%, 84%, 98%, and 99% in energy consumption for the STI, TNAND, TDecoder, TMUX, THA, and TMUL, respectively. Moreover, the noise immunity curve (NIC) and Monte Carlo analysis for major process variations (TOX, CNT Diameter, CNT's Count, and Channel length) were studied. The results confirmed that the third proposed THA3 and TMUL3 had higher strength and higher noise tolerance, among other designs. In addition, the second objective is using ternary data transmission to improve data communications between computer hosts. Also, this thesis proposes a bi-directional circuit that contains two converters: (1) A binary-to-ternary converter and (2) a ternary-to-binary converter. Finally, logical analysis and simulation results prove the merits of the approaches compared to existing designs in terms of transistor count, reduced latency, and energy efficiency. vi Contents Contents vii List of Tables xi List of Figures xiv Abbreviations xvii Symbols xix Appendix B CNFET-Based Designs of Ternary Half-Adder using a Novel "Decoderless" Ternary Multiplexer based on Unary Operators

Synthesis of Ternary Logic Circuits Using 2:1 Multiplexers

IEEE Transactions on Circuits and Systems I: Regular Papers, 2018

Traditionally, binary decision diagram (BDD)-based algorithms are used to synthesize binary logic functions. A BDD can be transformed into circuit implementation by replacing each node in the BDD with a 2:1 multiplexer. Similarly, a ternary decision diagram can be transformed into circuit implementation using 3:1 Multiplexers. In this paper, we present a novel synthesis technique to implement ternary logic circuits using 2:1 multiplexers. Initially a methodology, which transforms a ternary logic function into a ternary-transformed binary decision diagram, is presented. This methodology is the basis for the synthesis algorithm that is used to synthesize various ternary functions using 2:1 multiplexers. Results for various ternary benchmark functions indicate that the proposed algorithm results in circuits that have, on an average 79%, and up to 99% fewer transistors when compared with the most recent 3:1 multiplexer-based algorithm available in the literature. Synthesized circuits have been implemented using carbon-nanotube field-effect transistors and simulated in HSPICE.