Robust SAT-Based Search Algorithm for Leakage Power Reduction (original) (raw)

IJERT-Comparison of Various Leakage Power Reduction Techniques for CMOS Circuit Design

International Journal of Engineering Research and Technology (IJERT), 2013

https://www.ijert.org/comparison-of-various-leakage-power-reduction-techniques-for-cmos-circuit-design https://www.ijert.org/research/comparison-of-various-leakage-power-reduction-techniques-for-cmos-circuit-design-IJERTV2IS100167.pdf Power consumption is now a major technical problem facing the CMOS circuits in deep submicron process. As process moves to finer technologies, leakage power significantly increases very rapidly due to the high transistor density, reduced voltage and oxide thickness. We first experimentally investigate existing low-power techniques and point out problems with them. We then propose a family of circuit types for low-power design centered around inserting controlling transistors between pull-up and pull down circuits as well as between pull-up circuits/pull down circuits and power/ground.We have compared different approach, named “sleepy keeper,” which reduces leakage current while saving exact logic state. Sleepy keeper uses traditional sleep transistors plus two additional transistors – driven by a gate’s already calculated output – to save state during sleep mode. In short, like the sleepy stack approach, sleepy keeper achieves leakage power reduction equivalent to the sleep and other approaches but with the advantage of maintaining exact logic state (instead of destroying the logic state when sleep mode is entered).. Unfortunately, sleepy keeper causes additional dynamic power consumption, approximately 15% more than the base case (no sleep transistors used at all). However, for applications spending the vast majority of time in sleep or standby mode while also requiring low area, high performance and maintenance of exact logic state, the sleepy keeper approach provides a new weapon in a VLSI designer's arsenal

Modeling leakage power reduction in VLSI as optimization problems

Reducing power dissipation is one of the most important issues in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power dissipation. Multi-Threshold CMOS (MTCMOS) technology has emerged as a promising technique to reduce leakage power. This paper first introduces how to model the sleep transistor sizing problem in the MTCMOS circuits as a Bin-Packing Problem (BPP). The gate-clustering BPP and the First-Fit (FF) techniques are also introduced to further improve the solution quality. To take the circuit's routing complexity into consideration which is critical for Deep Sub-Micron (technologies that are 0.25 µm and below) (DSM) implementations, a Set-Partitioning Problem (SPP) is then formed. However, this highly constrained model limits it's application for large circuit design. A Set-Covering (SCP) model is therefore investigated to efficiently solve the problem.

Minimum leakage vector computation using weighted partial MaxSAT

2010

Aggressive scaling of CMOS technology has enabled faster and smaller designs but has posed new challenges. In the deep-submicron era, leakage power has become a major contributor to the overall power dissipation of an IC. In this paper, we present a weighted partial Max-SAT (WPMax-SAT) based approach to find the minimum leakage vector (MLV) of a combinational design. In its exact form, this technique computes the input vector which gives the lowest leakage for a combinational design. For large designs, the exact WPMax-SAT based technique may require large runtimes. Therefore, for such designs, the exact technique is run for a fixed amount of time followed by a guided random search around the best leakage vector computed by the WPMax-SAT solver. We also present a variant of our approach in which the MLV is generated by including the effect of random variations in leakage due to variations in process, voltage and temperature (PVT). Experimental results on ISCAS85 and MCNC91 benchmark circuits show that for larger circuits on average, our method reports a 3.62% improvement in mean, 4.20% improvement in standard deviation and 3.67% improvement in μ + 3*σ leakage of the circuit under PVT variations, compared to a random vector based MLV determination approach (with the same runtime as the random vector based approach).

LEAKAGE POWER REDUCTION TECHNIQUE IN CMOS CIRCUIT: A STATE-OF-THE-ART REVIEW

The demand for low power devices is increasing vastly due to the fast growth of battery operated applications such as smart phones and other handheld devices. It has become important to control the power dissipation throughout the design cycle beginning from the architectural level to final design at hardware level. Leakage current is the main factor which contributes to almost or more than 50% of total power dissipation. In many new high performance designs, the leakage component of power consumption is comparable to the switching component. More than 40% leakage in SRAM memory is due to leakage in transistors. This survey paper use the design of SRAM architecture to reduce the leakage current and hence the leakage power. The various leakage power reduction techniques have been evolved to tackle the problem and it is still in progress. In this paper mainly, there is study of various leakage power reduction techniques with SRAM architecture in fabrication Technology.

Leakage Power Reduction in CMOS Logic Circuit Using Various Techniques

https://www.ijrrjournal.com/IJRR\_Vol.9\_Issue.11\_Nov2022/IJRR-Abstract13.html, 2022

Low power nowadays High-power consumption has turned into a crucial design criterion for VLSI an emerging field. When it comes to energy efficiency, high power dissipation is not thought to be beneficial to battery life in the case of battery-powered applications. It reduces the efficiency, dependability, and cooling expenses of battery life. The high-frequency dynamic variation of inputs is heavily influenced by switching and short-circuit leakage power. There are several common methods for reducing the power consumption of circuits. The average power consumption consists of static and dynamic power consumption. The power consumption comparison of LECT0R, LCNT, Stack 0N0FIC, and SAP0N of various low-power techniques. These circuits are simulated in the cadence tool.

Comparative Analysis of Low Power and Low Leakage Reduction for Logic Circuits

IJEER, 2015

As technology scales in nanometer regime leakage current are becoming important metric of comparable importance to leakage current for the analysis and design of complex logic circuits. In this paper, we did the comparative analysis of leakage current for carry look ahead logic circuits. The simulation results depicts that the proposed design leads to efficient in terms of standby leakage power. We have performed simulations using Cadence Spectre 90nm standard CMOS technology at room temperature with supply voltage of 1V.

IJERT-Analysis of Leakage Power Reduction using Leakage Control Logic with Power Gating

International Journal of Engineering Research and Technology (IJERT), 2014

https://www.ijert.org/analysis-of-leakage-power-reduction-using-leakage-control-logic-with-power-gating https://www.ijert.org/research/analysis-of-leakage-power-reduction-using-leakage-control-logic-with-power-gating-IJERTV3IS070038.pdf In the world of VLSI Circuits, the semiconductor device length is quickly lowering. Attributable to this the leakage power dissipation has become associate preponderating concern. In this paper power reduction techniques are accustomed scale back power for D-Latch and SR Latch. These techniques involves leakage control Logic, leakage Feedback, sleepy Stacking and Stacking. leakage power is truly consumed once a tool is each static and change, however typically the most concern with leakage power is once the device is in its inactive state , as all the power consumed during this state is taken into account "wasted" power. Power gating which is employed as a basis of this idea is additionally a power reduction technique during which a further "sleep" PMOS transistor is placed between Vdd and also the pull up network of a circuit and a further "sleep" NMOS transistor is placed between the pull down network and GND. These circuits are turned on once the circuit is active and turned off once the circuit is off. Numerous techniques are developed to cut back power leakage. In this paper, the technique which is best in power consumption is obtained which concludes that leakage control logic is able to reduce power more efficiently than other techniques. We have performed the simulation and implementation of all the four above stated techniques on D-Latch and SR-Latch with the help of Tanner Tools.