Low Noise Wide Tuning Range Quadrature Ring Oscillator for Multi-Standard Transceiver (original) (raw)
A Cmos Ring Oscillator Vco with Quadrature Outputs and High-Tuning Range
2009
This paper presents the design of a new four-stage ring oscillator with quadrature outputs using a 0.13µm CMOS 1P8M technology. The oscillator utilizes feed-forward technique and negative resistance to reduce the delay per stage and provides high frequencies. Employing single PMOS transistor to vary the load impedance allows reaching ultra-wide tuning range. The output frequency ranges from 0.8 to 11.3 GHz, which is equivalent to nearly 175% tuning range, while the circuit consumes only 10mW. Simulation results illustrate a phase noise of-83dBc/Hz @ 1MHz offset from centre frequency. Also, the worst case phase variation due to mismatch is better than 0.4˚over the above frequency range.
Low-power high-tuning range CMOS ring oscillator VCOs
2008 IEEE International Conference on Semiconductor Electronics, 2008
This paper presents the design of two new ring oscillators based on differential and single-ended topologies using a 0.13µm 1P8M CMOS technology. The differential oscillator utilizes feed-forward technique and a new composite load with inductive impedance, reducing the delay per stage and widening the tuning range. The output frequency ranges from 0.5 to 9.5 GHz and the circuit consumes only 9mW. The simulation result of phase noise is -85.3dBc/Hz @ 1MHz offset from centre frequency. The singleended ring oscillator with inductive composite load oscillates from 6.3 to 13.9 GHz and consumes only 5.1 mW with phase noise of -81.5dBc/Hz @ 1MHz offset from centre frequency.
International Journal of Engineering Research and Applications, 2017
Voltage Controlled Oscillator is one of the most imperative blocks in the present communication system. It finds application in both wired as well as wireless communication as clock generator, frequency synthesizer and system synchronizer. The desirable characteristics of a VCO are high frequency, low phase noise, low power, low voltage and enhanced range of tuning. A three stage CMOS voltage controlled ring oscillator based on differential architecture and a LC tank voltage-controlled ring oscillator based on cross coupled architecture hasbeen designed by using 32nm and 90 nm technology respectively. The former VCO has a tuning range spanning from 733.718 MHz to 2.065 GHz with a phase noise of-79.4dBc/Hz while the latter possess better phase noise of-89.7dBc/Hz at the cost of reduced tuning range spanning from 4.5GHZ to 4.9GHZ only which is comparatively lesser than its counterpart.
Design and Analysis of 3 Stage Ring Oscillator Based on MOS Capacitance for Wireless Applications
This paper comprises the study and performance analysis of switched capacitor ring voltage controlled oscillator (VCO) which uses the method of controlling capacitance to regulate oscillation frequency. In this paper, three stage ring oscillator is designed based on added MOS capacitor in the output of each delay cell. 90 nm CMOS process technology has been used in simulation with the supply voltage of 1.8V whereas the variation of control voltage differs from 0V to 0.6V. A linear tuning characteristic has been achieved ranging from 4.52 GHz to 6.02 GHz in pursuit of wireless applications, specifically for IEEE 802.11a standard. The circuit shows very stable output waveform in different parameters with very low power consumption of 0.295 mW. The figure of merit (FoM) is-155.5 dBc/Hz and the phase noise is very reasonable considering the higher oscillation frequency of the circuit.
Design and analysis of wide tuning range differential ring oscillator (WTR-DRO)
Analog Integrated Circuits and Signal Processing, 2020
A new circuit of delay cell for differential ring oscillator (DRO), to generate wide tuning range, has been proposed. Two architectures of DRO: 3 stage and 4 stage, have been designed and simulated under the power supply constraint of 1.1 V, using GPDK 45 nm CMOS technology. Dual voltages are used to control the tuning frequency range in 3 stage DRO whereas single voltage control is used in 4 stage DRO. Tuning ranges of 351 MHz-30.33 GHz and 574 MHz-20.49 GHz, are generated using the proposed 3-stage and 4-stage DRO circuits, respectively. Total Harmonic Distortion of both circuits, is also measured through simulation. Power consumption of the proposed 3-stage and 4 stage DRO, are found to be 866 lW and 783 lW at an oscillation frequency of 2.77 GHz and 1.86 GHz, respectively. Proposed circuits exhibit phase noise of-96.7 dBc/Hz and-99.54 dBc/Hz at an offset of 10 MHz from the frequency of oscillation. Layout, is also drawn, occupies an area of 137.97 lm 2 and 170.34 lm 2 for 3 stage and 4 stage DRO, respectively. Robustness of the proposed circuits are verified across Process, Voltage and Temperature variations. The proposed DROs exhibit the largest tuning range when compared with the recent literature.
Development of Varied CMOS Ring Oscillator Topologies in 0.13-μm CMOS Technology
Applied Mechanics and Materials, 2013
This paper presents varied CMOS ring oscillator topologies using Silterra 0.13-µm Process. Three topologies of ring oscillators have been designed which is the single-ended ring oscillator, differential ring oscillator and ring oscillator based variable resistor for 2.4 GHz wireless applications. The proposed designs consist of five stages delay cell. The simulation results show that a single-ended ring oscillator obtained the lowest power consumption of 0.41 mW, while differential oscillator achieves phase noise of −64.44 dBc/Hz at 1 MHz offset frequency. However, ring oscillator based variable resistor did not achieve any significant improvement. The proposed design is oscillates at 2.4 GHz.
A wide tuning range, low noise oscillator with FoM of -188 dBc/Hz in 45 nm CMOS
AEU - International Journal of Electronics and Communications, 2020
A wide tuning range, low phase noise oscillator with 3 stage differential configuration is presented. GPDK 45 nm CMOS Technology is selected for the design and simulation of the proposed circuit, under power supply impediment of 1.1 V. Proposed delay cell features ultra wide tuning range as it utilizes dual control voltages (1 and 2), enabling large current to flow in the circuit. As frequency of oscillation has linear proportionality with the bias current, this oscillator generates frequencies from 534 MHz to 18.56 GHz. The proposed circuit occupies chip area of 102.87 μm 2. This circuit offers power consumption of 1.13 mWatt and phase noise of −108.61 dBc/Hz (10 MHz offset frequency) at 5.82 GHz oscillation frequency. Performance of the proposed circuit is evaluated on various temperature, supply voltage and process corners. Total Harmonic Distortion (THD) profile is also measured through simulation. Because of wide frequency spectrum, low phase noise, small area and low power budget, proposed circuit can be utilized in various power electronic applications, medical equipments, communication and navigation systems.
Multi-phase ring oscillator with minimized phase noise for ultra-wideband applications
2014 International Conference on Information Science, Electronics and Electrical Engineering, 2014
This paper presents the design of a simple multiphase ring oscillator (RO). It represents a new technique for RO output signal phase control. This RO uses a voltage injection principle to produce different phases output signal. The proposed RO consumes only 3.6 mW from a 1.8V power supply while having an oscillation frequency of 5.5 GHz with a 330 MHz fine tuning range. This RO is employing the pulse injection technique for phase noise enhancement. It has a phase noise less than -133.5 dBc/Hz @ 1 MHz offset. It achieves a figure of merit (FoM) of -182.75 dBc/Hz .This RO is designed and simulated in the standard 0.18 μm CMOS technology.
A 5.9 GHz Low Power and Wide Tuning Range CMOS Current-controlled Ring Oscillator
International Journal of Electrical and Computer Engineering (IJECE), 2012
Designing low power, low noise, wide tuning range and small size circuit in one single chip is very challenging. This paper describes alow power, wide tuning range three-stage current-controlled ring oscillator (CCO) which has been designedon 0.18µm CMOS technology. The CCO circuit has tuning range from 251 MHz to 5.5 GHz or it has tuning width 183%. Using 1.8V supply voltage, the CCO circuit consumes current from144 µA to 9.76mA. Phase noise is-104 dBc /Hz at 5.5 GHz and 4Mhz offset frequency. FoM is-154.4 dBc /Hz which is the best among published counterpart papers. The size of the core oscillator circuits without bonding pads is only 0.0003 mm 2 .
A Low Phase Noise CMOS Ring Oscillator Using Phase Modulation and Pulse Injection Techniques
This paper presents a novel design of a ring oscillator (RO) producing eight phases output with accurate signal phase adjustment. By using the pulse injection technique, the RO phase noise has been strongly suppressed. In addition, a novel phase control technique is proposed for the implementation of the phase modulation. The proposed RO achieves a phase noise of-131.5 dBc/Hz @1MHz offset and FoM of-199.25 dBc/Hz. This RO consumes a 3.4 mW of power from a 1.8V power supply while having an oscillation frequency of 4.5 GHz and a locking range of 540 MHz in CMOS 0.18 um technology.
2017
This Paper reports on design and analysis of CMOS Voltage Controlled Ring Oscillator (VCRO) based on the delay cells proposed by Changzhi Li and Jenshan Lin. The two stage CMOS VCRO exhibits very low power consumption and wide tuning range when realized using GPDK 45 nm CMOS process. The oscillator has a very wide tuning range from 6 GHz to 17 GHz. Because of its wide tuning range, it can be used for electronic warfare applications. It has also very low power consumption of about 3µW with a supply voltage of 1 V. The phase noise of this ring oscillator is found to be-78 dBC/Hz @10 MHz offset which can be improved by adding more number of stages.
A Low Phase Noise CMOS Ring Oscillator Using Phase Modulation and Pulse Injection Techniques (マイクロ波)
This paper presents a novel design of a ring oscillator (RO) producing eight phases output with accurate signal phase adjustment. By using the pulse injection technique, the RO phase noise has been strongly suppressed. In addition, a novel phase control technique is proposed for the implementation of the phase modulation. The proposed RO achieves a phase noise of -131.5 dBc/Hz @1MHz offset and FoM of -199.25 dBc/Hz. This RO consumes a 3.4 mW of power from a 1.8V power supply while having an oscillation frequency of 4.5 GHz and a locking range of 540 MHz in CMOS 0.18 um technology.
This project deals with the design and performance analysis of a ring oscillator using CMOS 180 nm technology process in Cadence virtuoso environment. The design of optimal Analog and Mixed Signal (AMS) very large scale integrated circuits (VLSI) is a challenging task for the integrated circuit(IC)designer. A Ring Oscillator is an active device which is made up of odd number of NOT gates and whose output oscillates between two voltage levels representing high and low. There are a number of challenges ahead while designing the CMOS Ring Oscillator which are delay, noise and glitches. CMOS is the technology of choice for many applications, CMOS oscillators with low power, phase noise and timing jitter are highly desired. In this project, we have designed a CMOS ring oscillator with nine stages. The researchers were unable to reduce the phase noise in ring oscillators substantially with nine stages. We have successfully reduced the phase noise to -6.4kdBc/Hz at 2GHz centre frequency of oscillation.
A 0.5 V Ultra-low Power Quadrature Ring Oscillator
IFIP Advances in Information and Communication Technology, 2014
In this paper we present a CMOS quadrature ring oscillator operating at 0.5 V. Due to this very low voltage conditions, new project technique using the available terminal of the transistors (bulk) is used in order to reduce the threshold voltage of the transistors, thus improving the voltage headroom. The technique is applied in a conventional inverter-based ring oscillator with a feedback topology capable to generate quadrature signals. Simulations results in a 130 nm CMOS technology shows that a very simple VCO in the GHz range can be obtained, by changing the bulk voltage of transistors (NMOS or PMOS). The circuit operates with less than 50 µW achieving a FoM of about-115 dBc/Hz at 10 MHz offset.
A Rigorous Phase Noise Analysis of Tuned Ring Oscillators
2007 IEEE Radio and Wireless Symposium, 2007
Tuned ring oscillators have found numerous applications due to their ability to generate multiple phases at high frequencies of operation while maintaining high signal purity. However, a comprehensive phase noise theory that explains the phase noise performance of tuned rings as a function of design parameters such as the number of elements and inter element phase shift is lacking. This paper rigorously builds such a theory and demonstrates that the phase noise improves by a factor of 10l100N as the number of elements (N) is increased. Further, the phase noise deteriorates (by a factor of 40loglocosAi at least) when the inter element phase shift AO is increased. In the context of multiple phase generation, under a fixed current budget, we demonstrate that it is beneficial to use a larger ring sizes. Extensive GHz-range simulations as well as measurements of prototype oscillators validate these claims.
A 7-GHz multiloop ring oscillator in 0.18-μm CMOS technology
Analog Integrated Circuits and Signal Processing, 2008
A novel delay stage for ring oscillator utilizing multiloop technique is presented in this paper. Different conventional delay stages for the multiloop ring oscillators have been reviewed and analyzed in this work. By using push-pull inverter as the secondary input in its delay cell, the proposed oscillator demonstrates a frequency improvement of up to 17% when compared with conventional designs. The fabricated oscillator is measured to cover a frequency range of 6.24-7.04 GHz. Operating in 1.8-V power supply, the oscillator manifests itself a phase noise of -107.7 dBc/Hz@10 MHz offset from a center frequency of 6.25 GHz. The proposed oscillator consumes a current of 40-51 mA from the 1.8-V supply and occupies an area of 440 lm 9 430 lm.
Phase noise in multi-gigahertz CMOS ring oscillators
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143)
An analysis of the phase noise in differential and singleended ring oscillators using a time-variant model is presented. An expression for the RMS value of the impulse sensitivity function (ISF) is derived. A closed-form equation for phase noise of ring oscillators is calculated and a lower limit on the phase noise of ring oscillators is shown. Phase noise measurements of oscillators running up to 5.5GHz are shown to be in good agreement with the theory.
IEICE Transactions on Electronics, 2010
A method to realize the fine frequency-tuning steps using tiny capacitors instead of Metal-Insulator-Metal (MIM) capacitors is proposed for a digitally controlled oscillator (DCO). The tiny capacitors are realized by the coplanar transmission lines which are arranged unsymmetrical in a 6 metal layers (M6) foundry of 0.18 μm CMOS technology. These transmission line based capacitors are designed by using electromagnetic field simulator, and co-designed by using SPICE simulator. Finally, these capacitors are employed to design 15 bit DCO and fabricated the proposed DCO in 0.18 μm CMOS technology, and tested. The measured phase noise of DCO was −118.3 dBc/Hz (@1 MHz offset frequency), and the oscillating frequency tuned from 4.86 GHz to 5.36 GHz in the minimum frequency-tuning step of 18 kHz. key words: digitally controlled oscillator, tiny capacitor, phase noise, frequency tuning step, 5-GHz-band wireless LAN, 0.18 μm CMOS
Design of a Wide-Band Voltage-Controlled Ring Oscillator Implemented in 180 nm CMOS Technology
Electronics, 2019
The design of a wide-band voltage-controlled oscillator (VCO) modified as a VCO with programmable tail currents is introduced herein. The VCO is implemented by using CMOS current-mode logic stages, which are based on differential pairs that are connected in a ring topology. SPICE simulation results show that the VCO operates within the frequency ranges of 2.65–5.65 GHz, and when it is modified, the VCO with programmable tail currents operates between 1.38 GHz and 4.72 GHz. The design of the CMOS differential stage is detailed along with the symbolic approximation of its dominant pole, which is varied to increase the frequency response in order to achieve a higher oscillation frequency when implementing the ring oscillator structure. The layout of the VCO is described and pre- and post-layout simulations are provided, which are in good agreement using CMOS technology of 180 nm. Finally, process, voltage and temperature variations are performed to guarantee robustness of the designed ...