Impact of MOSFET gate oxide breakdown on digital circuit operation and reliability (original) (raw)
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Gate oxide breakdown in FET devices and circuits: From nanoscale physics to system-level reliability
Microelectronics Reliability, 2007
Gate oxide breakdown has been historically considered a catastrophic failure mechanism for CMOS technology. With CMOS downscaling the mid 1990's have seen the emergence of soft breakdown as a possible failure mode. At the same time the notion started appearing that the first breakdown event does not necessarily spell the immediate failure of the entire CMOS application. Relaxation of the CMOS circuit reliability criteria, however, requires a thorough understanding of the impact of the breakdown path on FET behavior. This cannot be consistently achieved without the microscopic perspective of the physical effects occurring in the affected device. Future CMOS applications will be able to sustain many soft breakdown events, which will be treated as additional parametric variation. Tools ranging from simulation to circuit monitoring will assure reliability at the functional level.
Gate Oxide Wear-Out and Breakdown Effects on the Performance of Analog and Digital Circuits
IEEE Transactions on Electron Devices, 2008
To investigate the impact of gate oxide degradation and breakdown (BD) on complimentary metal-oxidesemiconductor circuit functionality, an accurate description of the electrical characteristics of the stressed devices, which can be included in circuit simulators, is needed. In this paper, a description of the stressed device performance that considers, on the one hand, the variation of the channel current and, on the other, the increase in the gate current due to the oxide degradation and BD is presented, which is able to account for different levels of oxide damage. The parameters extracted from device experimental data have been introduced in a circuit simulator to evaluate the effect of the oxide degradation and BD on simple analog (current mirror) and digital [reset set (RS) latches] circuits. The impact of the increase in the gate leakage current and the variation of the conduction along the metal-oxide-semiconductor field-effect transistor channel due to the oxide degradation on the circuit performances has been separately analyzed.
Digital Detection of Oxide Breakdown and Life-Time Extension in Submicron CMOS Technology
IEEE Transactions on Circuits and Systems I-regular Papers, 2008
In modern CMOS technologies reliability issues limit the maximum operating voltage of transistors. This prevents the integration of efficient power amplifiers (e.g., audio or RF) since stacked devices are needed to prevent breakdown, which reduces efficiency. Transistor reliability is strongly related to operating voltages; higher voltages result in faster degradation and hence in lower reliability and shorter life time. Degradation can be monitored by oxide degradation, threshold voltage-shifts and mobility reduction.
Prediction of Logic Product Failure Due To Thin-Gate Oxide Breakdown
2006
Gate oxide breakdown is a key mechanism limiting IC lifetime. Breakdown is typically characterized on test capacitors, but estimating product reliability from such results requires making a number of often-untested assumptions. This work compares the predictions of capacitor-based models to results from accelerated lifetest of logic CPU products. For the technology studied, lifetest failure rate was somewhat lower than model prediction, and failure analysis indicated that an important factor was the different sensitivities of logic circuits vs. cache cells and of n and p transistors in the cache. Analysis of the factors involved in determining oxide-breakdown reliability and of the statistical uncertainties in capacitor-based models indicates that it is important to calibrate models to product data including these effects. Once a model is validated, the paper discusses how it can be used to assess the reliability impact of changes in processing, use conditions, and circuit design.
The defect-centric perspective of device and circuit reliability—From gate oxide defects to circuits
Solid-State Electronics, 2016
As-fabricated (time-zero) variability and mean device aging are nowadays routinely considered in circuit simulations and design. Time-dependent variability (reliability-related variability) is an emerging concern that needs to be considered in circuit design as well. This phenomenon in deeply scaled devices can be best understood within the so-called defect-centric picture in terms of an ensemble of individual defects. The properties of gate oxide defects are discussed. It is further shown how in particular the electrical properties can be used to construct time-dependent variability distributions and can be propagated up to transistor-level circuits.
Encountering gate oxide breakdown with shadow transistors to increase reliability
2008
Device scaling has enabled continuous performance increase of integrated circuits. However, severe reliability and yield concerns are arising against the background of nanotechnology. Traditionally, most causes and countermeasures were solely considered manufacturing issues, but lately, we have seen a shift towards operational reliability issues. Though, besides intense research on soft-errors and system-level approaches very little effort is put into low-level design solutions in order to enhance lifetime reliability. Hence, we demonstrate that redundant transistor insertion does improve system reliability significantly as regards Time-Dependent Dielectric Breakdown (TDDB). Furthermore, we introduce an algorithm which identifies the transistors being most vulnerable to TDDB. Subsequently, redundant transistors (called shadow transistors) are inserted at the previously identified instances. Lastly, we argue for applying high threshold voltage devices for the redundant transistors. Finally, we present results for a set of benchmark circuits and prove the combined approach successful. The enhanced designs were on average 41.8 % more reliable compared to the initial designs in respect of TDDB at the price of moderately increased power consumption and delay.
Thin-Gate-Oxide Breakdown and CPU Failure-Rate Estimation
IEEE Transactions on Device and Materials Reliability, 2007
Gate-oxide breakdown is a key mechanism limiting IC lifetime. Lifetime is typically extrapolated from accelerated tests on test capacitors, but estimating product reliability from such results requires making a number of often-untested assumptions. This paper details a capacitor-based model and compares the predictions of the model to results from accelerated lifetest of actual logic CPU products, discussing the assumptions which make such a comparison necessary. For the technology studied, lifetest failure rate was somewhat lower than model prediction, and failure analysis indicated that important factors included the different sensitivities of logic circuits versus cache cells and of n and p transistors in the cache. Analysis of the factors involved in determining oxide-breakdown reliability and of the statistical uncertainties in capacitor-based models indicates that it is important to calibrate models to product data, including these effects. Once a model is validated, this paper discusses how it can be used to assess the reliability impact of changes in silicon processing and product use conditions.
Gate oxide reliability projection to the sub-2 nm regime
Semiconductor Science and Technology, 2000
The important components of reliability projection are investigated. Acceleration parameters are obtained for a 1.6 nm oxide with a soft breakdown criterion. Based on the physical percolation model, the voltage scaling factor for time to breakdown is found to increase with lower voltage, explaining the experimental observation of 6.7 ± 0.4 dec V −1 for the 1.6 nm oxide. The distribution of breakdown times is shown to be sensitive to thickness variation across the test wafer, and a Weibull slope of 1.38 ± 0.1 was obtained. The temperature dependence of the time to breakdown was found to be non-Arrhenius and to have a slope of 0.02 dec • C −1 . Using these parameters, the 1.6 nm oxide was found to have a 10 year lifetime with a 100 ppm failure rate for 1.3 V operation at 100 • C. Our understanding of soft breakdown is described as well as an investigation of device operation after soft breakdown, which may further improve the reliability projection.
A statistical approach for full-chip gate-oxide reliability analysis
International Conference on Computer Aided Design, 2008
Gate oxide breakdown is a key factor limiting the useful lifetime of an integrated circuit. Unfortunately, the conventional approach for full chip oxide reliability analysis assumes a uniform oxide-thickness for all devices. In practice, however, gate-oxide thickness varies from die-to-die and within-die and as the precision of process control worsens an alternative reliability analysis approach is needed. In this work,
IEEE Transactions on Electron Devices, 2004
This paper deals with the statistics of successive oxide breakdown (BD) events in MOS devices. Correlation effects between these successive events are experimentally related to the statistics of BD current jumps, thus suggesting that they are related to lateral propagation of the BD path. The application of the successive BD theory to chip reliability assessment is discussed. Several failure criteria and the related reliability methodologies are considered and some of their limits are established.