Single-Event Transient Analysis in High Speed Circuits (original) (raw)
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Single-Event Upset Analysis and Protection in High Speed Circuits
Eleventh IEEE European Test Symposium (ETS'06), 2006
The effect of Single-Event Transients (SETs) (at a combinational node of a design) on the system reliability is becoming a big concern for ICs manufactured using advanced technologies. An SET at a node of combinational part may cause a transient pulse at the input of a flip-flop and consequently is latched in the flip-flop and generates a soft-error. When an SET conjoined with a transition at a node along a critical path of the combinational part of a design, a transient delay fault may occur at the input of a flip-flop. On the other hand, increasing pipeline depth and using low power techniques such as multi-level power supply, and multi-threshold transistor convert almost all paths in a circuit to critical ones. Thus, studying the behavior of the SET in these kinds of circuits needs special attention. This paper studies the dynamic behavior of a circuit with massive critical paths in the presence of an SET. We also propose a novel flip-flop architecture to mitigate the effects of such SETs in combinational circuits. Furthermore, the proposed architecture can tolerant a Single Event Upset (SEU) caused by particle strike on the internal nodes of a flip-flop.
Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs)
2011
In this paper, we present a very fast and accurate technique to estimate the soft error rate of digital circuits in the presence of Multiple Event Transients (METs). In the proposed technique, called Multiple Event Probability Propagation (MEPP), a four-value logic and probability set are used to accurately propagate the effects of multiple erroneous values (transients) due to METs to the outputs and obtain soft error rate. MEPP considers a unified treatment of all three masking mechanisms ie, logical, electrical, and timing, while ...
Modeling Single Event Transients in Advanced Devices and ICs
IEEE Transactions on Nuclear Science
The ability for Single Event Transients (SETs) to induce soft errors in Integrated Circuits (ICs) was predicted for the first time by Wallmark and Marcus in the early 60’s and was confirmed to be a serious issue thirty years later. In the 90’s microelectronic technologies reached the “deep submicron” era, allowing high density ICs working at frequencies faster than hundreds of MHz. This new paradigm changed the status of SETs to become a major source of reliability losses. Huge efforts have thus been made to characterize SETs in microelectronics, either using experiments or by simulation, in order to reveal key factors leading to SET occurrence, propagation and capture in modern ICs. In this context, modeling and simulation are of primary importance to get accurate SET predictions. This paper focuses on modeling SETs in innovative electronic devices which involves modeling steps at different scales, from ionizing particle to circuit response. After a brief review of the state-of-the...
Modeling and Mitigating Transient Errors in Logic Circuits
IEEE Transactions on Dependable and Secure Computing, 2000
Transient or soft errors caused by various environmental effects are a growing concern in micro and nanoelectronics. We present a general framework for modeling and mitigating the logical effects of such errors in digital circuits. We observe that some errors have time-bounded effects; the system's output is corrupted for a few clock cycles, after which it recovers automatically. Since such erroneous behavior can be tolerated by some applications, i.e., it is noncritical at the system level, we define the critical soft error rate (CSER) as a more realistic alternative to the conventional SER measure. A simplified technology-independent fault model, the single transient fault (STF), is proposed for efficiently estimating the error probabilities associated with individual nodes in both combinational and sequential logic. STFs can be used to compute various other useful metrics for the faults and errors of interest, and the required computations can leverage the large body of existing methods and tools designed for (permanent) stuck-at faults. As an application of the proposed methodology, we introduce a systematic strategy for hardening logic circuits against transient faults. The goal is to achieve a desired level of CSER at minimum cost by selecting a subset of nodes for hardening against STFs. Exact and approximate algorithms to solve the node selection problem are presented. The effectiveness of this approach is demonstrated by experiments with the ISCAS-85 and -89 benchmark suites, as well as some large (multimillion-gate) industrial circuits.
Technologies, 2020
Integrated circuit susceptibility to radiation-induced faults remains a major reliability concern. The continuous downscaling of device feature size and the reduction in supply voltage in CMOS technology tend to worsen the problem. Thus, the evaluation of Soft Error Rate (SER) in the presence of multiple transient faults is necessary, since it remains an open research field. In this work, a Monte-Carlo simulation-based methodology is presented taking into consideration the masking mechanisms and placement information. The proposed SER estimation tool exploits the results of a Single Event Transient (SET) pulse characterization process with HSPICE to obtain an accurate assessment of circuit vulnerability to radiation. A new metric, called Glitch Latching Probability, which represents the impact of the masking effects on a SET, is introduced to identify gate sensitivity and, finally, experimental results on a set of ISCAS’ 89 benchmarks are presented.
SOFT ERROR RATE ESTIMATION FOR COMBINATIONAL LOGIC IN PRESENCE OF SINGLE EVENT MULTIPLE TRANSIENTS
Journal of Circuits, Systems and Computers, 2014
Fast and accurate estimation of soft error rate in VLSI circuits is an essential step in a soft error tolerant ASIC design. In order to have a cost e®ective protection against radiation e®ects in combinational logics, an accurate and fast method for identi¯cation of most susceptive gates and paths is needed. In this paper, an e±cient, fast and accurate method for soft error propagation probability (SEPP) estimation is presented and its performance is evaluated. This method takes into account all three masking factors in multi cycles. It also considers multiple event transients as a new challenge in soft error tolerant VLSI circuit design. Compared with Monte Carlo (MC) simulation-based fault injection method, our SEPP estimation method has a high level of accuracy (with less than 2% di®erence) while o®ering 1000Â speedup as compared with MC-based simulation.
Modeling, Analyzing, and Abstracting Single Event Transient Propagation at Gate Level
—Soft errors have become one of the most challenging issues that impact the reliability of modern microelectronic systems at terrestrial altitudes. A new methodology to abstract, model, and analyze Single Event Transient (SET) propagation at different abstraction levels (transistor and gate level) is proposed. Transistor level characterization libraries are developed to abstract the impact of input patterns, pulse polarity, and propagation paths characteristics on the SET duration. Thereafter, these libraries are utilized to analyze SET pulse propagation at gate level using MDG model checker. We have implemented the proposed method on different ISCAS85 benchmark combinational circuits. The proposed methodology is orders of magnitude faster than circuit level simulations. Moreover, we have developed gate level characterization libraries to abstract SET pulse propagation behavior at the gate level.
Efficient and Accurate Analysis of Single Event Transients Propagation Using SMT-Based Techniques
This paper presents a hierarchical framework to model, analyze , and estimate digital design vulnerability to soft errors due to Single Event Transients (SETs). A new SET propagation model is proposed. This model simultaneously includes the impact of masking effects, width variation, and re-converging paths by utilizing satisfiability modulo theories. Furthermore, new metrics characterizing the soft error rate of a given design are proposed. Reported results show that the proposed methodology significantly enhances the efficiency of SET analysis in terms of: 1) accuracy as it gives accurate estimates of SET sensitivity based on gates timing extracted from layout. These results provide new insights to combinational designs vulnerability to SETs; 2) speed as it is orders of magnitude faster than contemporary techniques; 3) scalability as it can handle large and complex designs such as 128-bit multipliers, whereas contemporary techniques are unable to handle multipliers larger than 32 bits.
Accurate and computer efficient modelling of single event transients in CMOS circuits
IET Circuits, Devices & Systems, 2007
A new analytical modelling approach to evaluate the impact of single event transients (SETs) on CMOS circuits has been developed. The model allows evaluation of transient pulse amplitude and width (duration) at the logic level, without the need to run circuit level (Spice-like) simulations. The SET mechanism in MOS circuits is normally investigated by Spice-like circuit simulation. The problem is that electrical simulation is time-consuming and must be performed for each different circuit topology, incident particle and track. The availability of a simple model at the logic gate level may greatly improve circuit sensitivity analysis. The electrical response of a circuit to an ionising particle hit depends on many parameters, such as circuit topology, circuit geometry and waveform shape of the charge injection mechanism. The proposed analytical model, which is accurate and computer efficient, captures these transistor-level effects of ionising particle hits and models them to the logic level of abstraction. The key idea is to exploit a model that allows the rapid determination of the sensitivity of any logic gate in a CMOS circuit, without the need to run circuit simulations. The model predicts whether or not a particle hit generates a SET, which may propagate to the next logic gate or memory element, making possible to analyse the sensitivity of each node in a complex circuit. Model derivation is strongly related to circuit electrical behaviour, being consistent with technology scaling. The model is suitable for integration into CAD tools, intending to make automated evaluation of circuit sensitivity to SET possible, as well as automated estimation of soft error rate.
Design-time reliability evaluation for digital circuits
2017
A new method of evaluating the reliability of combinational circuits is proposed, this method uses two levels of characterisation: a Stochastic Fault Model (SFM) of the component library and a design-specific Critical Vector Model (CVM). The idea is to move the high-complexity problem of stochastic characterisation of parameters into the generic part of the design process, and do it just once for a great number of the specific designs. The SFM captures variations of the vector of parameters of a library component fault model, those causing a transient fault at the component output; it is meant to be supplied by the foundry, similar to timing library files. The CVM is derived by a limited number of simulation runs on the specific design, and represents the boundary between the erroneous and error-free operation, w.r.t. the vector of parameters of each component. The probability of error-free operation is subsequently calculated by jointly using SFM and CVM. The method is demonstrated...