Modeling, Analyzing, and Abstracting Single Event Transient Propagation at Gate Level (original) (raw)
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Modeling Single Event Transients in Advanced Devices and ICs
IEEE Transactions on Nuclear Science
The ability for Single Event Transients (SETs) to induce soft errors in Integrated Circuits (ICs) was predicted for the first time by Wallmark and Marcus in the early 60’s and was confirmed to be a serious issue thirty years later. In the 90’s microelectronic technologies reached the “deep submicron” era, allowing high density ICs working at frequencies faster than hundreds of MHz. This new paradigm changed the status of SETs to become a major source of reliability losses. Huge efforts have thus been made to characterize SETs in microelectronics, either using experiments or by simulation, in order to reveal key factors leading to SET occurrence, propagation and capture in modern ICs. In this context, modeling and simulation are of primary importance to get accurate SET predictions. This paper focuses on modeling SETs in innovative electronic devices which involves modeling steps at different scales, from ionizing particle to circuit response. After a brief review of the state-of-the...
Accurate and computer efficient modelling of single event transients in CMOS circuits
IET Circuits, Devices & Systems, 2007
A new analytical modelling approach to evaluate the impact of single event transients (SETs) on CMOS circuits has been developed. The model allows evaluation of transient pulse amplitude and width (duration) at the logic level, without the need to run circuit level (Spice-like) simulations. The SET mechanism in MOS circuits is normally investigated by Spice-like circuit simulation. The problem is that electrical simulation is time-consuming and must be performed for each different circuit topology, incident particle and track. The availability of a simple model at the logic gate level may greatly improve circuit sensitivity analysis. The electrical response of a circuit to an ionising particle hit depends on many parameters, such as circuit topology, circuit geometry and waveform shape of the charge injection mechanism. The proposed analytical model, which is accurate and computer efficient, captures these transistor-level effects of ionising particle hits and models them to the logic level of abstraction. The key idea is to exploit a model that allows the rapid determination of the sensitivity of any logic gate in a CMOS circuit, without the need to run circuit simulations. The model predicts whether or not a particle hit generates a SET, which may propagate to the next logic gate or memory element, making possible to analyse the sensitivity of each node in a complex circuit. Model derivation is strongly related to circuit electrical behaviour, being consistent with technology scaling. The model is suitable for integration into CAD tools, intending to make automated evaluation of circuit sensitivity to SET possible, as well as automated estimation of soft error rate.
Single-Event Transient Analysis in High Speed Circuits
2011 International Symposium on Electronic System Design, 2011
The effect of Single-Event Transients (SETs) (at a combinational node of a design) on the system reliability is becoming a big concern for ICs manufactured using advanced technologies. An SET at a node of a combinational part of a circuit may propagate as a transient pulse at the input of a flip-flop and consequently latches in the flip-flop; thus generating a soft-error. When an SET is combined with a transition at a node (i.e., dynamic behavior of that node) along a critical path of the combinational part of a design, a transient delay fault may occur at the input of a circuit flip-flop. Using the Probability Density Function (PDF) of an SET, this paper proposes a statistical method to compute the probability of soft-errors caused by SETs considering dynamic behavior of a circuit.
Technologies, 2020
Integrated circuit susceptibility to radiation-induced faults remains a major reliability concern. The continuous downscaling of device feature size and the reduction in supply voltage in CMOS technology tend to worsen the problem. Thus, the evaluation of Soft Error Rate (SER) in the presence of multiple transient faults is necessary, since it remains an open research field. In this work, a Monte-Carlo simulation-based methodology is presented taking into consideration the masking mechanisms and placement information. The proposed SER estimation tool exploits the results of a Single Event Transient (SET) pulse characterization process with HSPICE to obtain an accurate assessment of circuit vulnerability to radiation. A new metric, called Glitch Latching Probability, which represents the impact of the masking effects on a SET, is introduced to identify gate sensitivity and, finally, experimental results on a set of ISCAS’ 89 benchmarks are presented.
Probabilistic Model Checking of Single Event Transient Propagation at RTL Level
Soft errors, induced by radiations, have a growing impact on the reliability of CMOS integrated circuits. The progressive shrinking of device sizes in advanced technologies leads to miniaturization and performance improvements. However, ultra-deep sub-micron technologies are more vulnerable to soft errors. In this paper, we propose a new methodology to model and analyze Single Event Transients (SETs) propagation at RTL level. Gate level characterization libraries are utilized to model the underlying probabilistic behavior of SET pulse propagation as Probabilistic Automata (PA). A probabilistic model checker is adapted to analyze the probability of SET pulse propagation for all injection scenarios. Experimental results are presented for different combinational circuits. Our proposed methodology is orders of magnitude faster than contemporary techniques that can be used to analyze SET pulse propagation probability.
Efficient and Accurate Analysis of Single Event Transients Propagation Using SMT-Based Techniques
This paper presents a hierarchical framework to model, analyze , and estimate digital design vulnerability to soft errors due to Single Event Transients (SETs). A new SET propagation model is proposed. This model simultaneously includes the impact of masking effects, width variation, and re-converging paths by utilizing satisfiability modulo theories. Furthermore, new metrics characterizing the soft error rate of a given design are proposed. Reported results show that the proposed methodology significantly enhances the efficiency of SET analysis in terms of: 1) accuracy as it gives accurate estimates of SET sensitivity based on gates timing extracted from layout. These results provide new insights to combinational designs vulnerability to SETs; 2) speed as it is orders of magnitude faster than contemporary techniques; 3) scalability as it can handle large and complex designs such as 128-bit multipliers, whereas contemporary techniques are unable to handle multipliers larger than 32 bits.
IEEE Transactions on Nuclear Science, 2000
This paper presents a SET predictive methodology based on coupled MUSCA SEP3 and electrical simulations (CA-DENCE tool). The method is validated by SET measurements on an inverters chain based on 65-nm bulk CMOS technology, and two designs were considered (respectively for same-well and separate-well designs). These methodologies have been validated in the case of 1000 inverters chain and for heavy ions and demonstrate the impact of the quenching effect. Furthermore, both the designs were considered and the analyses are consistent with experiments and this allows for identification of the quenching effect as the main mechanism responsible for the difference in SET sensitivity. However, the modeling approach can be also used for other logical cells or/and complex radiation environments, to determine SET cross sections, SET cartographies and SET characteristics. This method is applied to SEU analyses, i.e., SBU (Single Bit Upset) and MCU (Multiple Cell Upset) for 65-nm bulk SRAM memory and neutron/proton SET modeling.
Towards Formal Abstraction, Modeling, and Analysis of Single Event Transients at RTL
Soft errors due to Single Event Transients (SETs) have become one of the most challenging issues that impact the reliability of modern microelectronic systems at terrestrial altitudes. This is mainly due to the progressive shrinking of device sizes. Traditionally, the analysis of SETs has been carried out by simulations and experimental analysis. However, these techniques are resource hungry and require full details of the design structure and SET characteristics. This paper develops a hierarchical framework for formal analysis of SET propagation by (1) introducing Register Transfer Level (RTL) abstraction and modeling approaches of the underlying behavior of SET propagation using Multiway Decision Graphs (MDGs); and (2) investigating SET propagation conditions at RTL using a formal model checker. In order to illustrate the practical utilization of our work, we have analyzed different RTL combinational designs. Experimental results demonstrate the proposed framework is orders of magnitude faster than other comparable contemporary techniques. Moreover, for the first time, a decision graph based technique is developed to analyze multiplier designs.
Single Event Transients in Logic Circuits—Load and Propagation Induced Pulse Broadening
IEEE Transactions on Nuclear Science, 2008
The generation and propagation of single event transients (SET) in logic gate chains is studied and modeled. Regarding SET generation, we investigate the dependence of the generated SET pulse width on the struck node capacitance. Rising node capacitance may lead to amplified pulse width, indicating that increasing load capacitance alone is not an option for radiation hardening. SET propagation in logic chains is also studied, and it is shown that significant broadening or attenuation of the propagated transient pulse width may be observed. It is shown that the chain design (propagation delay of high to low and low to high transitions) has a major impact on broadening or attenuation of the propagated transient pulse. For the first time a suitable model for SET broadening is provided.
Modeling the sensitivity of CMOS circuits to radiation induced single event transients
Microelectronics Reliability, 2008
An accurate and computer efficient analytical model for the evaluation of integrated circuit sensitivity to radiation induced single event transients is presented. The key idea of the work is to exploit a model that allows the rapid determination of the sensitivity of any MOS circuit to single event transients (SETs), without the need to run circuit level simulations. To accomplish this task, both single event transient generation and its propagation through circuit logic stages are characterized and modeled. The model predicts whether or not a particle hit generates a transient pulse which may propagate to the next logic gate or memory element. The electrical masking (attenuation) of the transient pulse as it propagates through each stage of logic until it reaches a memory element is also modeled. Model derivation is in strong relation with circuit electrical behavior, being consistent with technology scaling. The model is suitable for integration into CAD-Tools, intending to make automated evaluation of circuit sensitivity to SEU possible.