Continuous deep reactive ion etching of tapered via holes for three-dimensional integration (original) (raw)
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Cryogenic inductively coupled plasma etching for fabrication of tapered through-silicon vias
Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films, 2010
Vertical interconnects pose an interesting method for heterogeneous integration of electronic technologies allowing three-dimensional ͑3D͒ stacking of microelectromechanical systems devices and integrated circuit components. The vertical interconnects, referred to as through-silicon vias, begin with the formation of blind vias in silicon that are eventually exposed by mechanically lapping and polishing the wafer back side. Inductively coupled plasma ͑ICP͒ etching using SF 6 / O 2 gas chemistry at cryogenic temperatures has been investigated as a way to form vias with a tapered sidewall. The point in creating a controlled taper is so that subsequent thin films can be deposited along the sloped sidewall that line the via with insulation, barrier, and seed films. This tapering is necessary if the via lining processes do not provide adequate conformal coverage, a common problem for conventional low temperature deposition processes. In our process for lining the via sidewall, plasma enhanced chemical vapor deposited silicon dioxide is used to insulate vias from the surrounding silicon. Both Ti and Cu are sputter deposited and provide protection from copper migration and a seed film for Cu electrodeposition, respectively. After etching and lining, the vias are filled by reverse pulse plating of Cu. Vias are 20-25 m in diameter and etched using different masking materials. The effect of changing gas flow rates, chamber pressure, ICP power, and substrate temperature on etch rate, via profile, and sidewall morphology will be presented. These parameters are critical in the optimization of an etch process for vias of specific dimensions to be used in 3D integration.
Inductively coupled plasma etching of tapered via in silicon for MEMS integration
Microelectronic Engineering, 2015
An ICP plasma etching technique for fabrication of tapered vias on silicon substrates has been developed by means of single patterning and etching process. Experimentally, effects of parameters including ICP power, chamber pressure, gas ratio and RF bias power were investigated for their impact on etch rate, selectivity, profile and surface roughness. Monotonic profile angles in the range of 60-80°have been achieved on 10-50 lm wide vias through adjustment of the C 4 F 8 /SF 6 ratio and optimization on other key parameters. We found that addition of O 2 controlled lateral etch rate only weakly, except when running the process at cryogenic temperature. Adjustment of the process powers was a significant factor in controlling sidewall roughness.
Development of vertical and tapered via etch for 3D through wafer interconnect technology
2006 8th Electronics Packaging Technology Conference, 2006
Two types of dry silicon etch techniques are developed to cover two different areas of demand for interconnect technology: one for high aspect ratio (AR) vertical vias and one for tapered vias. Various sizes of vertical vias and trenches with diameters/widths ranging from 1-100 µm with an AR up to 50 are realized using Bosch Deep Reactive Ion Etch (DRIE) process. A linear model is applied to describe and to give physical insight in the Aspect Ratio Dependant Etch (ARDE) effect. The feasibility of the vertical vias as electrical interconnect is shown by isolating them from the substrate by silicon oxide and then filling with polysilicon. The tapered vias are typically post-processed on fabricated device wafers, making it inherently a more generic approach where diameter size can be large and low AR can be tolerated. Vias with a depth of ~100 µm and a diameter of ~50 µm at the bottom (though larger at top) are realized. Varying various etch parameters, slope angles of 70°-80° are realized to allow for conformal deposition of dielectric/seed materials on the sidewalls and to allow lithography within the via. Reactive Ion Etch (RIE) is used to fabricate sloped vias by simultaneously applying etch and passivation gasses. Negative angles on the via top and sidewall roughness are observed that introduce conformal coating problems and increased leakage currents.
2002
This paper presents guidelines for the deep reactive ion etching (DRIE) of silicon MEMS structures, employing SF 6 O 2-based high-density plasmas at cryogenic temperatures. Procedures of how to tune the equipment for optimal results with respect to etch rate and profile control are described. Profile control is a delicate balance between the respective etching and deposition rates of a SiO F passivation layer on the sidewalls and bottom of an etched structure in relation to the silicon removal rate from unpassivated areas. Any parameter that affects the relative rates of these processes has an effect on profile control. The deposition of the SiO F layer is mainly determined by the oxygen content in the SF 6 gas flow and the electrode temperature. Removal of the SiO F layer is mainly determined by the kinetic energy (self-bias) of ions in the SF 6 O 2 plasma. Diagrams for profile control are given as a function of parameter settings, employing the previously published "black silicon method". Parameter settings for high rate silicon bulk etching, and the etching of micro needles and micro moulds are discussed, which demonstrate the usefulness of the diagrams for optimal design of etched features. Furthermore it is demonstrated that in order to use the oxygen flow as a control parameter for cryogenic DRIE, it is necessary to avoid or at least restrict the presence of fused silica as a dome material, because this material may release oxygen due to corrosion during operation of the plasma source. When inert dome materials like alumina are used, etching recipes can be defined for a broad variety of microstructures in the cryogenic temperature regime. Recipes with relatively low oxygen content (1-10% of the total gas volume) and ions with low kinetic energy can now be applied to observe a low lateral etch rate beneath the mask, and a high selectivity (more than 500) of silicon etching with respect to polymers and oxide mask materials is obtained. Crystallographic preference etching of silicon is observed at low wafer temperature (120 C). This effect is enhanced by increasing the process pressure above 10 mtorr or for low ion energies (below 20 eV). [720] Index Terms-Cryogenic etching, profile control, reactive ion etching (RIE).
Plasma Etching of Tapered Features in Silicon for MEMS and Wafer Level Packaging Applications
Journal of Physics: Conference Series, 2006
This paper is a brief report of plasma etching as applied to pattern transfer in silicon. It will focus more on concept overview and strategies for etching of tapered features of interest for MEMS and Wafer Level Packaging (WLP). The basis of plasma etching, the dry etching technique, is explained [1] and plasma configurations are described elsewhere [2][3]. An important feature of plasma etching is the possibility to achieve etch anisotropy. The plasma etch process is extremely sensitive to many variables such as mask material, mask openings and more important the plasma parameters.
Deep Vertical Etching of Silicon Wafers Using a Hydrogenation-Assisted Reactive Ion Etching
Journal of Microelectromechanical Systems, 2000
A novel hydrogenation-assisted deep reactive ion etching of silicon is reported. The process uses sequential hydrogen-assisted passivation and plasma etching at low-density plasma powers to stimulate the vertical removal of the exposed Si substrate. The main feature of this technique is the sequential alternation of the electrodes while switching between different gases. Three-dimensional structures with aspect ratios in excess of 40 : 1 and features as small as 0.7 µm have been realized. The net etch rate is about 0.25 µm/min, although higher rates are expected to be achievable.
A survey on the reactive ion etching of silicon in microtechnology
Journal of Micromechanics and Microengineering, 1996
This article is a brief review of dry etching as applied to pattern transfer, primarily in silicon technology. It focuses on concepts and topics for etching materials of interest in micromechanics. The basis of plasma-assisted etching, the main dry etching technique, is explained and plasma system configurations are described such as reactive ion etching (RIE). An important feature of RIE is its ability to achieve etch directionality. The mechanism behind this directionality and various plasma chemistries to fulfil this task will be explained. Multi-step plasma chemistries are found to be useful to etch, release and passivate micromechanical structures in one run successfully. Plasma etching is extremely sensitive to many variables, making etch results inconsistent and irreproducible. Therefore, important plasma parameters, mask materials and their influences will be treated. Moreover, RIE has its own specific problems, and solutions will be formulated. The result of an RIE process depends in a non-linear way on a great number of parameters. Therefore, a careful data acquisition is necessary. Also, plasma monitoring is needed for the determination of the etch end point for a given process. This review is ended with some promising current trends in plasma etching.