A flexible simulation methodology and tool for nanoarray-based architectures (original) (raw)

Fault tolerant nanoarray circuits: Automatic design and verification

2014 IEEE 32nd VLSI Test Symposium (VTS), 2014

We automatically maximize fault-tolerance in nanoarrays based on silicon nanowires and Gate-All-Around transistors optimizing their topology vs. several distributions of faults inherited by technology. We added a MonteCarlo engine in our nanoarchitecture design tool ToPoliNano and verified the effectiveness of the fault-tolerance algorithm over several circuits and faults distributions. 1

Nanoarray architectures multilevel simulation

ACM Journal on Emerging Technologies in Computing Systems, 2014

Testing Nanoarrays Fault Tolerance

2013

The interesting expectations on nanoarray based circuits are counterbalanced by critical issues related to reliability. Nanowires and active devices currently cannot rely on a mature technology and high rates of defects are still to be expected. Our approach to evaluate the effects on nanoarray based circuits behavior consists in simulating at switch level the precise behavior of the circuit considering a statistical distribution of faults throughout the tile area. We are able to reckon the output error rate of nanoarray circuits as a function of defective rates and defect distribution giving to both technologists and architects directions to find possible solutions

Developing Fault Models for Nanowire Logic Circuits

… at IEEE Int. Conf. on Dependable …

It is widely acknowledged that nanoelectronic devices will suffer from more manufacturing and operational faults than classical CMOS devices in large-scale integrated circuits. The confident use of these emerging technologies relies on our capacity to better understand their fault mechanisms, and our ability to deduce related fault models. These challenging goals are addressed in this paper for nanowire logic circuits, which constitute one of the most promising technologies in the nanoelectronics realm. Fault models are proposed attending to how fault mechanisms manifest at device and logic abstraction levels. This research is framed within a more global investigation focused on the development of suitable dependability assessment methodologies and defect and fault tolerance strategies for systems built-up using nanodevices.

Enabling design and simulation of massive parallel nanoarchitectures

Journal of Parallel and Distributed Computing, 2014

A common element in emerging nanotechnologies is the increasing complexity of the problems to face when attempting the design phase, because issues related to technology, specific application and architecture must be evaluated simultaneously. In several cases faced problems are known, but require a fresh rethink on the basis of different constraints not enforced by standard design tools. Among the emerging nanotechnologies, the two-dimensional structures based on nanowire arrays is promising in particular for massively parallel architectures. Several studies have been proposed on the exploration of the space of architectural solutions, but only a few derived high-level information from the results of an extended and reliable characterization of low-level structures. The tool we present is of aid in the design of circuits based on nanotechnologies, here discussed in the specific case of nanowire arrays, as best candidate for massively parallel architectures. It enables the designer to start from a standard High-level Description Languages (HDL), inherits constraints at physical level and applies them when organizing the physical implementation of the circuit elements and of their connections. It provides a complete simulation environment with two levels of refinement. One for DC analysis using a fast engine based on a simple switch level model. The other for obtaining transient performance based on automatic extraction of circuit parasitics, on detailed device (nanowire-FET) information derived by experiments or by existing accurate models, and on spice-level modeling of the nanoarray. Results about the method used for the design and simulation of circuits based on nanowire-FET and nanoarray will be presented.

Fault-tolerant programmable logic array for nanoelectronics

International Journal of Circuit Theory and Applications, 2012

This paper presents the architecture for a nanoelectronic logic system in which a regular array of logic gates with programmable interconnections is accompanied by a data transmitter and receiver as well as program registers and a controller. Binary programmable interconnections assure system versatility by providing the means of computing different logic operations. They also allow setting the redundancy level via the number of columns clustered to compute a certain function. A system operation is explained and visualized with a number of examples. The embedded scheme of fault tolerance can effectively mitigate permanent, as well as transient, faults. Some implementation and performance aspects are approached through simulations of single-electron tunneling structures. However, the proposed architectural concept is generic and can be applied to systems implemented with alternative nanotechnologies.

A BIST Approach for Configurable Nanofabric Arrays

2008 8th IEEE Conference on Nanotechnology, 2008

This work proposes a Built-in Self Test (BIST) approach to test crossbars for a defined set of faults. The BIST can classify the different programmable elements in the crossbars as non-defective or defective with a certain fault type. The logic synthesis can then configure the crossbar by avoiding these defective elements.

Evaluation of Design Strategies for Stochastically Assembled Nanoarray Memories

A key challenge facing nanotechnologies is learning to control uncertainty introduced by stochastic self-assembly. In this article, we explore architectural and manufacturing strategies to cope with this uncertainty when assembling nanoarrays, crossbars composed of two orthogonal sets of parallel nanowires (NWs) that are differentiated at their time of manufacture. NW deposition is a stochastic process and the NW encodings present in an array cannot be known in advance. We explore the reliable construction of memories from stochastically assembled arrays. This is accomplished by describing several families of NW encodings and developing strategies to map external binary addresses onto internal NW encodings using programmable circuitry. We explore a variety of different mapping strategies and develop probabilistic methods of analysis. This is the first article that makes clear the wide range of choices that are available.

Fault-Tolerant Nanoscale Processors on Semiconductor Nanowire Grids

IEEE Transactions on Circuits and Systems I-regular Papers, 2007

Nanoscale processor designs pose new challenges not encountered in the world of conventional CMOS designs and manufacturing. Nanoscale devices based on crossed semiconductor nanowires (NWs) have promising characteristics in addition to providing great density advantage over conventional CMOS devices. This density advantage could, however, be easily lost when assembled into nanoscale systems and especially after techniques dealing with high defect rates and manufacturing related layout/doping constraints are incorporated. Most conventional defect/fault-tolerance techniques are not suitable in nanoscale designs because they are designed for very small defect rates and assume arbitrary layouts for required circuits. Reconfigurable approaches face fundamental challenges including a complex interface between the micro and nano components required for programming. In this paper, we present our work on adding fault-tolerance to all components of a processor implemented on a 2-D semiconductor nanowire (NW) fabric called NASICs. We combine and explore structural redundancy, built-in nanoscale error correcting circuitry, and system-level redundancy techniques and adapt the techniques to the NASIC fabric. Faulty signals caused by defects and other error sources are masked on-the-fly at various levels of granularity. Faults can be masked at up to 15% rates, while maintaining a 7X density advantage compared to an equivalent CMOS processor at projected 18nm technology. Detailed analysis of yield, density, and area tradeoffs is provided for different error sources and fault distributions.

Logic synthesis and testing techniques for switching nano-crossbar arrays

Microprocessors and Microsystems, 2017

Beyond CMOS, new technologies are emerging to extend electronic systems with features unavailable to silicon-based devices. Emerging technologies provide new logic and interconnection structures for computation, storage and communication that may require new design paradigms, and therefore trigger the development of a new generation of design automation tools. In the last decade, several emerging technologies have been proposed and the time has come for studying new ad-hoc techniques and tools for logic synthesis, physical design and testing. The main goal of this project is developing a complete synthesis and optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. New models for diode, FET, and four-terminal switch based nanoarrays are developed. The proposed methodology implements logic, arithmetic, and memory elements by considering performance parameters such as area, delay, power dissipation, and reliability. With combination of logic, arithmetic, and memory elements a synchronous state machine (SSM), representation of a computer, is realized. The proposed methodology targets variety of emerging technologies including nanowire/nanotube crossbar arrays, magnetic switch-based structures, and crossbar memories. The results of this project will be a foundation of nano-crossbar based circuit design techniques and greatly contribute to the construction of emerging computers beyond CMOS. The topic of this project can be considered under the research area of "Emerging Computing Mod

A flexible simulation methodology and tool for nanoarray-based architectures (original) (raw)

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