Development and Implementation of C4NP Technology for 300 mm Wafers (original) (raw)
Related papers
C4NP technology: Manufacturability, yields and reliability
2008 58th Electronic Components and Technology Conference, 2008
As a part of IBM movement from Pb-rich solders to Pbfree solder, a new low cost process has been developed to deposit the solder to a capture, or under bump metal (UBM) pad, with Suss MicroTech Inc as the equipment partner. The controlled collapsed chip connection new process (C4NP) has moved, over the last 2 years, from development into manufacturing for 300 mm wafers. During this transition, a great number of process improvements have resulted in high fabrication yields. Manufacturing robustness has been achieved by clearly identifying the processes which affect the C4 structural integrity. The solder composition has been optimized to improve its mechanical properties as well as low alpha emission rate requirement.
C4NP Technology for Lead Free Solder Bumping
2007 Proceedings 57th Electronic Components and Technology Conference, 2007
C4NP is a novel solder bumping technology developed by IBM that addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. It is a solder transfer technology where molten solder is injected into prefabricated and reusable glass molds. The glass mold contains etched cavities which mirror the bump pattern on the wafer. Filled mold and wafer are brought into close proximity/soft contact at reflow temperature and solder bumps are transferred onto the entire 300mm (or smaller) wafer in a single process step without the complexities associated with liquid flux. The simplicity of the process makes it a low cost, high yield and fast cycle time solution for bumping with a variety of high performance lead free alloys. The focus of this paper is on the mold fabrication, solder fill and inspection steps prior to solder transfer including high volume manufacturing tool designs. Yield improvements from the mold suppliers and mold specs are discussed. Finally, the results from a detailed cost model are reviewed. This cost model includes a comparison of C4NP versus alternative bumping techniques and includes capital, materials, and labor cost factors.
C4NP - data for fine pitch to CSP flip chip solder bumping
2006 8th Electronics Packaging Technology Conference, 2006
To meet future requirements for cost, size, weight and electrical performance, microelectronic packaging is moving from wire bonds to solder bumps as the preferred method of interconnection from the device to the chip carrier or card. Flip chip in Package (FCiP) requires many small bumps on tight pitch whereas Wafer Level Chip Scale Packaging (WLCSP) typically requires much larger solder bumps on a greater pitch. Electroplating, solder paste printing and the direct attach of preformed solder spheres are technologies commonly used in volume production. Each of these techniques has limitations in scaling from fine pitch FCiP to WLCSP. Electroplating is better suited to fine pitch, whereas solder paste printing and solder sphere attachment work well for coarser pitches. C4NP (Controlled Collapse Chip Connection New Process) has proven to be suitable for this entire range of solder bump pitch. C4NP is a new solder bumping technology developed by IBM and commercialized by Suss MicroTec. C4NP addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. C4NP is a solder transfer technology where molten solder is injected into prefabricated and reusable glass templates (molds). The filled mold is inspected prior to solder transfer to the wafer to ensure high final yields. Filled mold and wafer are brought into close proximity/contact and solder bumps are transferred onto the entire 300mm (or smaller) wafer in a single process step without the complexities associated with liquid flux. C4NP technology is capable of fine pitch bumping while offering the same alloy selection flexibility as solder paste printing. The simplicity of the C4NP process makes it a low cost, high yield and fast cycle time solution for both, fine-pitch FCiP as well as WLCSP bumping applications. This paper summarizes the latest manufacturing and reliability data for high-end logic device packaging using 300mm wafers bumped with C4NP. This includes reliability data for C4NP lead free solder bumped devices attached to organic chip carriers. Mold fill data for CSP type dimensions is included. Solder metrology data and yield information for fine pitch applications is summarized. Relevant process equipment technology and the unique requirements to run a high volume manufacturing C4NP process are reviewed. The paper also summarizes the C4NP manufacturing cost model and elaborates on the cost comparison to alternative bumping techniques.
Assembly, Characterization, and Reworkability of Pb-free UltraFine Pitch C4s for System-on-Package
2007
As chip I/O count continues to increase, the C4 bump pitch needs to be further reduced. In this work, a Si-based test carrier was used for characterization of ultra-fine pitch micro C4s. Successful assembly and rework of die with 11,892 micro C4s were demonstrated. The micro C4 contact resistance was measured for various pad geometries. The mechanical shear force was characterized for several variables including contact pad area, pad shape, and shear direction. When joined onto pads with reduced size, the micro C4s were sheared without significant damage. Therefore, a carrier with reduced-size bonding pads can be utilized as a platform for functional test and burn-in followed by chip removal to create know-good-die (KGD). These high I/O KGD can be joined to a multi-chip module, silicon package or stacked to create chip stacks and tested to create known-good-modules (KGM) or known-good-die-stacks (KGDS). This specialized high I/O silicon carrier with full area array, reduced-area bonding pads is also referred to as a temporary chip attachment (TCA) substrate.
Characterization of micro-bump C4 interconnects for Si-carrier SOP applications
2006
This paper describes yield, contact resistance, and preliminary reliability test results on micro-bump C4 interconnects in modules containing Si-chips and Si-carriers. Modules containing eutectic PbSn or SnCu bump solders were fabricated with high yield, with similar interconnect contact resistances for both solders. The contact resistance and reliability test results to date suggest that reliable, high-current, high-density bump interconnections can be achieved for Si-carrier technology
C4NP Cu-cored Pb-free flip chip interconnections
2008 58th Electronic Components and Technology Conference, 2008
We report here preliminary results on a new Cu-cored flip chip structure combining C4NP (Controlled Collapse Chip Connect New Process) with Cu spheres for high density interconnections. C4NP is a new wafer bumping technology developed by IBM in which molten solder is injected into a mold and then transferred to the UBM (Under Bump Metallurgy) pads on the wafer. This simple and parallel process has shown the capability to combine low cost attributes with high performance capabilities. C4NP allows a larger number of interconnections with finer pitch than screen printing methods because it eliminates the volume reduction problem of solder paste. Also, C4NP allows more freedom in selecting the composition of solder bumps when compared with the electroplating method.
50μm pitch Pb-free micro-bumps by C4NP technology
2008 58th Electronic Components and Technology Conference, 2008
Controlled collapse chip connection new process (C4NP) is currently used in IBM manufacturing for all 300 mm Pbfree wafer bumping for flip chip packages. In this study, the extendibility of C4NP technology to ultra fine pitch applications has been explored. Reusable C4NP glass molds were fabricated and characterized for 50µm pitch application. Mold fill and wafer transfer with Pb-free solders have been demonstrated using both 200mm and 300mm wafers in a manufacturing environment. Significant improvement in bump yield was achieved for these early demonstations of fine pitch interconnections through process optimization and contamination control. Challenge in wafer inspection metrology is discussed for the 50µm pitch micro-bumps. Mechanical strength of the C4NP micro-bumps has been characterized using test dies with a full area array of microbumps.
International Symposium on Microelectronics, 2011
Leadless, near chip scale packages (LNCSP) like the quad flat pack no lead (QFN) are the fastest growing package types in the electronics industry today. Early LNCSPs were fairly straightforward components with small overall dimensions, a single outer row of leads and small lead counts. However, there is currently a proliferation of advanced LNCSP package styles that have started to approach BGA packages in terms of both size and number of connections. Some of the newer packages have 3 or more rows, pitches as fine as .35mm, lead counts exceeding 200, and dimensions exceeding 12 mm × 12 mm. While the advantages of these packages are well documented, concerns arise with both reliability and manufacturability in Pb-free environments. So, acceptance of these packages in long-life, severe-environment, high-reliability applications is somewhat limited. One of the most common drivers for reliability failures is the inappropriate adoption of new technologies like LNCSP. Since robust manufa...
3D chip stacking with C4 technology
IBM Journal of Research and Development, 2000
Three-dimensional (3D) integration technology promises to continue enhancing integrated-circuit system performance with high bandwidth, low latency, low power, and a small form factor for a variety of applications. In this work, conventional C4 (controlled-collapse chip connection) technology is studied for robust interconnection between stacked thin chips. Various solder hierarchies to enable 3D chip stacking and packaging are investigated. Examples are presented to compare stacking schemes with sequential and parallel reflow. Chips as thin as 90 lm are stacked using conventional chip-placement and reflow processes, and the associated process challenges are investigated and discussed. Warpage of the thin chips is measured on various substrates. Rework of the chip stack has also been demonstrated through a temporary chip attachment operation, and the scalability of reworkable C4 is investigated.