Analytical Optimization Of Signal Delays in VLSI Placement (original) (raw)

Min-max placement for large-scale timing optimization

2002

Abstract At the 250nm technology node, interconnect delays account for over 40% of worst delays [12]. Transition to 130nm and below increases this figure, and hence the relative importance of timing-driven placement for VLSI. Our work introduces a novel minimization of maximal path delay that improves upon previously known algorithms for timing-driven placement. Our placement algorithms have provable properties and are fast in practice.

Optimality and stability study of timing-driven placement algorithms

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486), 2003

This work studies the optimality and stability of timing-driven placement algorithms. The contributions of this work include two parts: 1) We develop an algorithm for generating synthetic examples with known optimal delay for timing driven placement (T-PEKO). The examples generated by our algorithm can closely match the characteristics of real circuits. 2) Using these synthetic examples with known optimal solutions, we studied the optimality of several timing-driven placement algorithms for FPGAs by comparing their solutions with the optimal solutions, and their stability by varying the number of longest paths in the examples. Our study shows that with a single longest path, the delay produced by these algorithms is from 10% to 18% longer than the optima on the average, and from 34% to 53% longer in the worst case. Furthermore, their solution quality deteriorates as the number of longest paths increases. For examples with more than 5 longest paths, their delay is from 23% to 35% longer than the optima on the average, and is from 41% to 48% longer in the worst case.

An Effective Timing-Driven Detailed Placement Algorithm for FPGAs

Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

In this paper, we propose a new timing-driven detailed placement technique for FPGAs based on optimizing critical paths. Our approach extends well beyond the previously known critical path optimization approaches and explores a significantly larger solution space. It is also complementary to single-net based timing optimization approaches. The new algorithm models the detailed placement improvement problem as a shortest path optimization problem, and optimizes the placement of all elements in the entire timing critical path simultaneously, while minimizing the costs of adjusting the placement of adjacent non-critical elements. Experimental results on industrial circuits using a modern FPGA device show an average placement clock frequency improvement of 4.5%.

Simultaneous delay and power optimization in global placement

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

Delay and power minimization are two important objectives in the current circuit designs. Retiming is a very effective way for delay optimization for sequential circuits. In this paper we propose a framework for multi-level global placement with retiming, targeting simultaneous delay and power optimization. We propose GEO-P for power optimization and GEO-PD algorithm for simultaneous delay and power optimization and provide smooth wirelength, power and delay tradeoff. In GEO-PD, we use retiming based timing analysis and visible power analysis to identify timing and power critical nets and assign proper weights to them to guide the multi-level optimization process. We show an effective way to translate the timing and power analysis results from the original netlist to a coarsened subnetlist for effective multi-level delay and power optimization. Our GEO-P achieves 27% average power improvement and our GEO-PD provides gains in both delay and power improvement. To the best of our knowledge, this is the first paper addressing simultaneous delay and power optimization in multi-level global placement.

Local search for final placement in vlsi design

2001

A new heuristic is presented for the general cell placement problem where the objective is to minimize total bounding box netlength. The heuristic is based on the Guided Local Search (GLS) metaheuristic. GLS modifies the objective function in a constructive way to escape local minima. Previous attempts to use local search on final (or detailed) placement problems have often failed as the neighborhood quickly becomes too excessive for large circuits. Nevertheless, by combining GLS with Fast Local Search it is possible to focus the search on appropriate sub-neighborhoods, thus reducing the time complexity considerably.

Progress and Challenges in VLSI Placement Research

2012

ABSTRACT Given the significance of placement in IC physical design, extensive research studies performed over the last 50 years addressed numerous aspects of global and detailed placement. The objectives and the constraints dominant in placement have been revised many times over, and continue to evolve. Additionally, the increasing scale of placement instances affects the algorithms of choice for high-performance tools.

Improving placement under the constant delay model

Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition, 2000

In this paper, we show that under the constant delay model the placement problem is equivalent to minimizing a weighted sum of wire lengths. The weights can be efficiently computed once in advance and still accurately reflect the circuit area throughout the placement process. The existence of an efficient and accurate cost function allows us to directly optimize circuit area. This leads to better results compared to heuristic edge weight estimates or optimization for secondary criteria such as wire length. We leverage this property to improve a recursive partitioning based tool flow. We achieve area savings of 27% for some circuits and 15% on average. The use of the constant delay model additionally enables timing closure without iterations.

Ca & Sbo : A Novel Optimized Placement Algorithms for an Efficient Vlsi Design

Designing a simplest architecture involves appropriate placement, which is often, regarded as a critical concerns of physical design engineers. Placement and routing of chips in automated manner is been research since decades and provides better predictive performance than manual procedures. However, most of the automated models operating under meta-heuristic optimization fails in obtaining optimal solution due to premature convergence and non-optimal placement of solutions. In this paper, we develop a novel meta-heuristic optimization method namely Cellular Automata (CA) and Satin Bowerbird Optimization (SBO) that combines Primal-dual lagrangian technique (SimPL) and Complex Primal dual lagrangian (ComPL) for attaining optimal placement and routing of chips. The process of CA and SBO optimization approach operates on obtaining optimized placement solutions from the SimPL and ComPL solutions. The combination of CA-SimPL, SBO-SimPL, CA-ComPL and SBO-ComPL is implemented on electronic...

Guided local search for final placement in VLSI design

Journal of Heuristics, 2003

ANUPLACE: A SYNTHESIS AWARE VLSI PLACER TO MINIMIZE TIMING CLOSURE

In Deep Sub Micron (DSM) technologies, circuits fail to meet the timings estimated during synthesis after completion of the layout which is termed as ‘Timing Closure’ problem. This work focuses on the study of reasons for failure of timing closure for a given synthesis solution. It was found that this failure is due to non-adherence of synthesizer’s assumptions during placement. A synthesis aware new placer called ANUPLACE was developed which adheres to assumptions made during synthesis. The new algorithms developed are illustrated with an example. ANUPLACE was applied to a set of standard placement benchmark circuits. There was an average improvement of 53.7% in the Half-Perimeter-Wire-Lengths (HPWL) with an average area penalty of 12.6% of the placed circuits when compared to the results obtained by the existing placement algorithms reported in the literature.

Analytical Optimization Of Signal Delays in VLSI Placement (original) (raw)

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