Improving min-cut placement for VLSI using analytical techniques (original) (raw)

Partitioning-based Methods for VLSI Placement

2008

The technique of using balanced min-cut partitioning in placement was presented by Breuer in 1977 [7]. Such min-cut placers use scalable and extensible divide-and-conquer algorithmic framework and tend to produce routable placements [9]. Recent work offers extensions to block placement and large-scale mixed-size placement [15, 18, 31], and robust incremental placement [33].

Progress and Challenges in VLSI Placement Research

2012

ABSTRACT Given the significance of placement in IC physical design, extensive research studies performed over the last 50 years addressed numerous aspects of global and detailed placement. The objectives and the constraints dominant in placement have been revised many times over, and continue to evolve. Additionally, the increasing scale of placement instances affects the algorithms of choice for high-performance tools.

Local search for final placement in vlsi design

2001

A new heuristic is presented for the general cell placement problem where the objective is to minimize total bounding box netlength. The heuristic is based on the Guided Local Search (GLS) metaheuristic. GLS modifies the objective function in a constructive way to escape local minima. Previous attempts to use local search on final (or detailed) placement problems have often failed as the neighborhood quickly becomes too excessive for large circuits. Nevertheless, by combining GLS with Fast Local Search it is possible to focus the search on appropriate sub-neighborhoods, thus reducing the time complexity considerably.

Optimality and Scalability Study of Existing Placement Algorithms

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2004

Placement is an important step in the overall IC design process in DSM technologies, as it defines the on-chip interconnects, which have become the bottleneck in determining circuit performance. The rapidly increasing design complexity, combined with the demand for the capability of handling nearly flattened designs for physical hierarchy generation, poses significant challenges to existing placement algorithms. There are very few studies on understanding the optimality and scalability of placement algorithms, due to the limited sizes of existing benchmarks and limited knowledge of optimal solutions. The contribution of this paper includes two parts: 1) We implemented an algorithm for generating synthetic benchmarks that have known optimal wirelengths and can match any given net distribution vector. 2) Using benchmarks of 10K to 2M placeable modules with known optimal solutions, we studied the optimality and scalability of three state-of-the-art placers, Dragon [4], Capo [1], mPL [24] from academia, and one leading edge industrial placer, QPlace [5] from Cadence. For the first time our study reveals the gap between the results produced by these tools versus true optimal solutions. The wirelengths produced by these tools are 1.66 to 2.53 times the optimal in the worst cases, and are 1.46 to 2.38 times the optimal on the average. As for scalability, the average solution quality of each tool deteriorates by an additional 4% to 25% when the problem size increases by a factor of 10. These results indicate significant room for improvement in existing placement algorithms.

Guided local search for final placement in VLSI design

Journal of Heuristics, 2003

A new heuristic is presented for the general cell placement problem where the objective is to minimize total bounding box netlength. The heuristic is based on the Guided Local Search (GLS) metaheuristic. GLS modifies the objective function in a constructive way to escape local minima. Previous attempts to use local search on final (or detailed) placement problems have often failed as the neighborhood quickly becomes too excessive for large circuits. Nevertheless, by combining GLS with Fast Local Search it is possible to focus the search on appropriate sub-neighborhoods, thus reducing the time complexity considerably.

Analytical Optimization Of Signal Delays in VLSI Placement

2002

Abstract In analytical placement, one seeks locations of circuit modules that optimize an objective function, but allows module overlaps. Our work introduces a novel minimization of maximal path delay that improves upon previously known algorithms for timing-driven placement. Our placement algorithms have provable properties and are fast in practice.

A Degree-Based Clustering Technique for VLSI Placement

Journal of Algorithms & Computational Technology, 2009

In this paper, clustering for the circuit placement problem is examined from the perspective of wire length contribution from groups of nets. First, the final wire length data of groups of nets with different degrees are extracted and studied. It is illustrated that nets with high-degree contribute a high percentage to the total wire length. To remedy this problem, a clustering algorithm for placement is proposed that focuses on clustering nets with high-degree. This new clustering algorithm is implemented as a preprocessing step in the placement stage. ICCAD04 benchmark circuits abstracted from IBM are used to validate the placement quality by using four academic placers with and without the proposed preprocessing step. Experiments show that the overall placement results can be improved by up to 5%.

Multi-level placement for large-scale mixed-size IC designs

Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC, 2003

In this paper we study the large-scale mixed-size placement problem where there is a significant size variation between big and small placeable objects (the ratio can be as large as 10,000). We develop a multi-level optimization algorithm, MPG-MS, for this problem which can efficiently handle both large-scale designs and large size variations. Compared with the recently published work [1] on large-scale mixed macro and standard cell placement benchmarks for wirelength minimization, our method can achieve 13% wirelength reduction on average with comparable runtime.

FPGA placement using space-filling curves: Theory meets practice

ACM Transactions on …, 2009

Research in VLSI placement, an NP-hard problem, has branched in two different directions. The first one employs iterative heuristics with many tunable parameters to produce a near-optimal solution but without theoretical guarantee on its quality. The other one considers ...

Ca & Sbo : A Novel Optimized Placement Algorithms for an Efficient Vlsi Design

Designing a simplest architecture involves appropriate placement, which is often, regarded as a critical concerns of physical design engineers. Placement and routing of chips in automated manner is been research since decades and provides better predictive performance than manual procedures. However, most of the automated models operating under meta-heuristic optimization fails in obtaining optimal solution due to premature convergence and non-optimal placement of solutions. In this paper, we develop a novel meta-heuristic optimization method namely Cellular Automata (CA) and Satin Bowerbird Optimization (SBO) that combines Primal-dual lagrangian technique (SimPL) and Complex Primal dual lagrangian (ComPL) for attaining optimal placement and routing of chips. The process of CA and SBO optimization approach operates on obtaining optimized placement solutions from the SimPL and ComPL solutions. The combination of CA-SimPL, SBO-SimPL, CA-ComPL and SBO-ComPL is implemented on electronic...