Advanced polymer systems for optoelectronic integrated circuit applications (original) (raw)

H E Wlett-packar D Journal Technical Information from the Hewlett-packard Company Journal the Hewlett-packard Journal Staff Advisory Board Communications Challenges of the Digital Information Utility Optical Networks: Backbones for Universal Connectivity ^2^ Data Transmission for Higher- Speed Ieee

1997

An artistic rendition of global internet commu nications, showing fiber optic technology as the backbone for universal connectivity. We are approaching an era in which people will need 1-Gbit/s communica tions ports in their offices, their homes, and even on the road. These high speed tele-ports will enable telecommuting, telemedicine, tele-education, and a variety of multimedia applications for entertainment and computing. These demands for high-speed communications will require new telecommunications and data communications infrastructure with terabit/s data rates. Additionally, these communications networks will require very high-speed computers (Tflops), very high-speed instrumentation (THz), and large information storage (Tbytes). The technologies needed to reach these rates are being worked on at many R&D organizations around the world. In fact, many demonstrations have been completed in 1996-1997 showing 1-Tbii/s communications links over more than 100 kilometers, 1-Tflops co...

Analysis and implementation of optoelectronic network routers

1999

Network routers based on optoelectronic technology have the potential to solve the network bandwidth problem which is becoming more and more critical in multiprocessor systems. By combining high-bandwidth optoelectronic I/O technology and high-performance CMOS logic technology, optoelectronic network routers promise both sophisticated switching functions as well as ample bandwidth that scales well with the performance of current and next-generation processors. Performance analysis and implementation of optoelectronic routers or other optoelectronic chips with this level of complexity, however, have not been pursued to a great extent before. This dissertation uses analytical and semi-empirical models to quantify and estimate the performance of optoelectronic routers at the chip and system levels, and it studies the feasibility of implementing such routers using GaAs MESFET/LED/OPFET and CMOS/SEED integrated technologies. The results show that optoelectronic routers may not only be technologically viable but also can provide certain architectural advantages in multiprocessor systems. Nevertheless, as shown in this dissertation, three major requirements must be met to effectively utilize this new technology. First, small and robust packaging at the chip and system levels that ensure high-bandwidth operation at useful interconnection distances and topologies are needed. Second, optoelectronic compatible CAD tools that effectively integrate a large array of optoelectronic devices with complex circuitry while retaining the potential performance of optoelectronic chips are needed. Third, optoelectronic devices must have uniform characteristics and reliability. In addition, advanced architectural techniques that efficiently exploit high-bandwidth optical interconnects are also required.

Parallel optical interconnects with mixed-signal OEIC and fibre arrays for high-speed communication

2004

We present a system for direct parallel optical data communication between integrated circuits on neighboured printed circuit boards based on a monolithic integrated CMOS smart pixel array, fibre arrays, and VCSELs. The advantage of our system versus backplane systems is the direct data transfer through the space avoiding planar and area consuming interconnections. The detector chip allows a data rate of 625 Mbit/s per link and is cycled by an optical clock. A simulation of the chip layout showed 260 % more performance versus electrical off-chip interconnects. In principle an 8'8 data transfer is feasible allowing a data rate of 40 Gbit/s. The detector combines an optical receiver array with a digital processor array which executes image processing algorithms. The optical receiver is formed by a PIN photodiode with a diameter of 40 μm, a transimpedance amplifier (TIA) and a decision-making postamplifier. The measured responsivity of the photodiode without antireflection coating is R=0.382 A/W at an optical wavelength of 670 nm. The TIA consists of a CMOS inverter and a PMOS transistor forming the feedback resistor. Together with the postamplifier, formed by a chain of five CMOS inverters and attaining digital CMOS levels, a data rate of 625 Mbit/s is achieved.