Orientation dependence of the charge distribution and quantum capacitance in silicon nanowire transistors (original) (raw)
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—In this work we have investigated the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future applications. For the purpose of this paper we have simulated Si NWTs with six different cross-section shapes. However for all devices the cross-sectional area is kept constant in order to provide fair comparison. Additionally we have expanded the computational experiment by including different gate length and gate materials for each of these six Si NWTs. As a result we have established a correlation between the mobile charge distribution in the channel and gate capacitance, drain induced barrier lowering (DIBL) and the sub-threshold slope (SS). The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also have been investigated. More importantly all calculations are based on quantum mechanical description of the mobile charge distribution in the channel. This description is based on Schrödinger equation, which is indeed mandatory for nanowires with such ultra-scale dimensions.
Bandstructure and mobility variations in p-type silicon nanowires under electrostatic gate field
Solid-State Electronics, 2013
The sp 3 d 5 s * -spin-orbit-coupled atomistic tight-binding (TB) model is used for the electronic structure calculation of Si nanowires (NWs), self consistently coupled to a 2D Poisson equation, solved in the cross section of the NW. Upon convergence, the linearized Boltzmann transport theory is employed for the mobility calculation, including carrier scattering by phonons and surface roughness. As the channel is driven into inversion, for [111] and [110] NW devices of diameters D>10nm the curvature of the bandstructure increases and the hole effective mass becomes lighter, resulting in a ~50% mobility increase. Such improvement is large enough to compensate for the detrimental effect of surface roughness scattering. The effect is very similar to the bandstructure variations and mobility improvement observed under geometric confinement, however, in this case confinement is caused by electrostatic gating. We provide explanations for this behavior based on features of the heavy-hole band. This effect could be exploited in the design of p-type NW devices. We note, finally, that the "apparent" mobility of low dimensional short channel transistors is always lower than the intrinsic channel diffusive mobility due to the detrimental influence of the so called "ballistic" mobility.
In this paper we have studied the impact of quantum confinement on the performance of n-type silicon nanowire transistors (NWT) for application in advanced CMOS technologies. The 3D drift-diffusion simulations based on the density gradient approach that has been calibrated with respect to the solution of the Schrödinger equation in 2D cross-sections along the direction of the transport are presented. The simulated NWTs have cross-sections and dimensional characteristics representative of the transistors expected at 7nm CMOS technology. Different gate lengths, cross-section shapes, spacer thicknesses and doping steepness were considered. We have studied the impact of the quantum corrections on the gate capacitance, the mobile charge in the channel, the drain-induced barrier lowering and the sub-threshold slope. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs is also investigated. We have also estimated the optimal gate length for different NWT design conditions.
In this work we investigate the correlation between channel strain and device performance in various n-type Si-NWTs. We establish a correlation between strain, gate length and cross-section dimension of the transistors. For the purpose of this paper we simulate Si NWTs with a <110> channel orientation, four different ellipsoidal channel cross-sections and five gate lengths: 4nm, 6nm, 8nm, 10nm and 12nm. We have also analyzed the impact of strain on drain-induced barrier lowering (DIBL) and the subthreshold slope (SS). All simulations are based on a quantum mechanical description of the mobile charge distribution in the channel obtained from a 2D solution of the Schrödinger equation in multiple cross sections along the current path, which is mandatory for nanowires with such ultra-scale dimensions. The current transport along the channel is simulated using 3D Monte Carlo (MC) and drift-diffusion (DD) approaches.
This work reveals the impact of quantum mechanical effects on the device performancce of n-type silicon nanowire transistors (NWT). Here we present results for two Si NWTs with circular and elliptical cross-section. Additionally we designed both devices to have identical cross-section in order to provide fair comparison. Also we extended our discussions by reporting devices with five different gate lengths for both circular and elliptical nanowires. Our calculations gave us the opportunity to establish a link between the charge distribution in the channel, gate capacitance, drain induced barrier lowering (DIBL) and the sub-threshold slope (SS). We also performed two types of calculations considering two different theoretical approaches. First one is based on drift-diffusion (DD) without quantum correction. The second one is constructed on quantum mechanical (QM) description of the mobile charge distribution in the channel. The QM methodology is based on Schr??dinger equation. More importantly, in this work showw that capturing the QM effects is mandatory for nanowires with such ultra-scale dimensions.
We present a simulation study of Si nanowire (NW) transistor devices for logic applications using an atomistic tightbinding (TB) model for the electronic structure calculation, self consistently coupled to a two-dimensional Poisson solver for the solution of the electrostatics. A semiclassical ballistic model is used for the transport calculation. The average carrier velocity and the capacitance of cylindrical NMOS and PMOS NWs with diameters from 3nm to 12nm, in the [100], [110] and [111] transport orientations are calculated at different gate bias. The capacitance of all wires is only a function of the wires' diameter, and in all cases is degraded from the oxide capacitance by ~20%. The carrier velocities increase with increasing gate biases. The carrier velocity of PMOS NWs in the [110] and [111] orientations is a strong function of the wires' diameter, whereas that of [100] and [111] NMOS and [100] PMOS devices has only a weak dependence on the diameter.
Physical Review B, 2009
An atomistic full-band quantum transport simulator has been developed to study three-dimensional Si nanowire field-effect transistors in the presence of electron-phonon scattering. The nonequilibrium Green's function ͑NEGF͒ formalism is solved in a nearest-neighbor sp 3 d 5 s ء tight-binding basis. The scattering selfenergies are derived in the self-consistent Born approximation to inelastically couple the full electron and phonon energy spectra. The band dispersion and the eigenmodes of the confined phonons are calculated using a dynamical matrix that includes the bond and the angle deformations of the nanowires. The optimization of the numerical algorithms and the parallelization of the NEGF scheme enable the investigation of nanowire structures with diameters up to 3 nm and lengths over 40 nm. It is found that the reduction in the device drain current, caused by electron-phonon scattering, is more important in the ON state than in the OFF state of the transistor. Ballistic transport simulations considerably overestimate the device ON currents by artificially increasing the charge injection mechanism at the source contact.
Phys Rev B, 2011
A simulation framework that couples atomistic electronic structures to Boltzmann transport formalism is developed and applied to calculate the transport characteristics of thin silicon nanowires (NWs) up to 12 nm in diameter. The sp3d5s*-spin-orbit-coupled atomistic tight-binding model is used for the electronic structure calculation. Linearized Boltzmann transport theory is applied, including carrier scattering by phonons, surface roughness (SRS), and impurities. We present a comprehensive investigation of the low-field mobility in silicon NWs considering i) n- and p-type NWs, ii) [100], [110], and [111] transport orientations, and iii) diameters from D = 12 nm (electronically almost bulk-like) down to D = 3 nm (ultra-scaled). The simulation results display strong variations in the characteristics of the different NW types. For n-type NWs, phonon scattering and SRS become stronger as the diameter is reduced and drastically degrade the mobility by up to an order of magnitude depending on the orientation. For the [111] and [110] p-type NWs, on the other hand, large mobility enhancements (on the order of ˜4×) can be achieved as the diameter scales down to D = 3 nm. This enhancement originates from the increase in the subband curvatures as the diameter is scaled. It overcompensates for the mobility reduction caused by SRS in narrow NWs and offers an advantage with diameter scaling. Our results may provide understanding of recent experimental measurements, as well as guidance in the design of NW channel devices with improved transport properties.
Quantum-mechanical analysis of the electrostatics in silicon-nanowire and carbon-nanotube FETs
Solid-state Electronics, 2006
In this work we investigate the electrostatics of the top-gate carbon-nanotube FET (CNT-FET) and the silicon-based P-gate FET at the ITRS 22 nm node. In order to do so, we solve the coupled Schrö dinger and Poisson equations within the cross-section of each device, and compare the channel-charge and capacitance curves as functions of the gate voltage. This study shows that, for a fixed cross-sectional area, the quantitative differences between the two devices are small both in terms of charge and capacitance. The use of a classical model for the P-gate FET shows instead that the resulting discrepancies with respect to the quantum-mechanical (QM) model are very relevant using both the Boltzmann and Fermi statistics. Thus, accounting for quantum-mechanical effects is essential for a realistic prediction of the device on-current and transconductance at the feature sizes considered here. The effect of high-j dielectrics is also addressed. As opposed to planar-gate devices, the electrostatic performance of Si-based P-gate FETs and CNT-FETs is not adversely affected by the use of different insulating materials with the same equivalent oxide thickness. As a consequence, not only do high-j dielectrics relieve the gate-leakage problem; they also improve the device performance in terms of the gate-control effectiveness over the channel.