Impact of strain on the performance of Si nanowires transistors at the scaling limit: A 3D Monte Carlo / 2D Poisson Schrodinger simulation study (original) (raw)
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—In this work we have investigated the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future applications. For the purpose of this paper we have simulated Si NWTs with six different cross-section shapes. However for all devices the cross-sectional area is kept constant in order to provide fair comparison. Additionally we have expanded the computational experiment by including different gate length and gate materials for each of these six Si NWTs. As a result we have established a correlation between the mobile charge distribution in the channel and gate capacitance, drain induced barrier lowering (DIBL) and the sub-threshold slope (SS). The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also have been investigated. More importantly all calculations are based on quantum mechanical description of the mobile charge distribution in the channel. This description is based on Schrödinger equation, which is indeed mandatory for nanowires with such ultra-scale dimensions.
Strain effects on transport properties of Si nanowire devices
We study the effects of strains on the performances of 001 and 110 oriented gate-all-around silicon nanowire (Si NW) transistors within a Non-Equilibrium Green's Functions framework. In agreement with previous works, we show that uniaxial strains can significantly improve the carrier mobility in the channel. However, we find that besides the enhancement of the carrier mobility, the ballistic resistance must be simultaneously optimized to achieve good performances in short channel devices. The response of the ballistic resistance to strains is different in [001] and [110] strained devices. Our study shows that the ballistic resistance is improved more consistently with the mobility in [110] Si NWs, providing the best opportunities for strain engineering in ultimate short channel transistors.
Simulation Study of Vertically Stacked Lateral Si Nanowires Transistors for 5 nm CMOS Applications
— In this paper we present a simulation study of vertically stacked lateral nanowires transistors (NWTs), which may have applications at 5nm CMOS technology. Our simulation approach is based on a collection of simulation techniques to capture the complexity in such ultra-scaled devices. Initially, we used drift-diffusion methodology with activated Poisson-Schrodinger quantum corrections to accurately capture the quantum confinement in the cross-section of the device. Ensemble Monte Carlo simulations are used to accurately evaluate the drive current capturing the complexity of the carrier transport in the NWTs. We compared the current flow in single, double, and triple vertically stacked lateral NWTs with and without contact resistance. The results presented here suggest a consistent link between channel strain and device performance. Furthermore, we propose a device structure for the 5nm CMOS technology node that meets the required industry scaling projection. We also consider the interplay between various sources of statistical variability and reliability in this paper.
Three-dimensional simulation of one-dimensional transport in silicon nanowire transistors
IEEE Transactions on Nanotechnology, 2007
We present a simulation study of silicon nanowire transistors, based on an in-house code providing the self-consistent solution of Poisson, Schrödinger, and continuity equations on a generic three-dimensional domain. The main assumption, based on the very small nanowire cross section considered, is that an adiabatic approximation can be applied to the Schrödinger equation, so that transport occurs along one-dimensional subbands. Different subband transport models are considered, such as ballistic transport, either including quantum tunneling or not, and drift-diffusion. We show that nanowire transistors exhibit good control of short channel effects, and that barrier tunneling is significant in the strong inversion regime even for longer devices, while it is significant in subthreshold only for the shortest channel lengths. Finally, we show that a subband-based transport model allows to reach a very good trade off between physical accuracy of the simulation and computing time.
In this paper we have studied the impact of quantum confinement on the performance of n-type silicon nanowire transistors (NWT) for application in advanced CMOS technologies. The 3D drift-diffusion simulations based on the density gradient approach that has been calibrated with respect to the solution of the Schrödinger equation in 2D cross-sections along the direction of the transport are presented. The simulated NWTs have cross-sections and dimensional characteristics representative of the transistors expected at 7nm CMOS technology. Different gate lengths, cross-section shapes, spacer thicknesses and doping steepness were considered. We have studied the impact of the quantum corrections on the gate capacitance, the mobile charge in the channel, the drain-induced barrier lowering and the sub-threshold slope. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs is also investigated. We have also estimated the optimal gate length for different NWT design conditions.
2008
Abstract CMOS devices are evolving from planar to 3D non-planar devices at nanometer scale to meet the ITRS [1] scaling requirements. These devices will operate under strong confinement and strain, regimes where atomistic effects are important. This work focuses on the quantum effects on the electrostatics of ultra-scaled silicon nanowire transistors. The method is based on the calculation of nanowire dispersion using an atomistic tight-binding (TB) model (sp3d5s*-SO) coupled self-consistently to a 2D Poisson equation solver.
One-dimensional multi-subband Monte Carlo simulation of charge transport in Si nanowire transistors
2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2016
In this paper, we employ a newly-developed one-dimensional multi-subband Monte Carlo (1DMSMC) simulation module to study electron transport in nanowire structures. The 1DMSMC simulation module is integrated into the GSS TCAD simulator GARAND coupling a MC electron trajectory simulation with a 3D Poisson-2D Schrödinger solver, and accounting for the modified acoustic phonon, optical phonon, and surface roughness scattering mechanisms. We apply the simulator to investigate the effect of the overlap factor, scattering mechanisms, material and geometrical properties on the mobility in silicon nanowire field-effect transistors (NWTs). This paper emphasizes the importance of using 1D models that include correctly quantum confinement and allow for a reliable prediction of the performance of NWTs at the scaling limits. Our simulator is a valuable tool for providing optimal designs for ultra-scaled NWTs, in terms of performance and reliability.
Simulations of gated Si nanowires and 3-nm junctionless transistors
2010
Inspired by recent experimental realizations and theoretical simulations of thin silicon nanowirebased devices, we perform predictive first-principles simulations of junctionless gated Si nanowire transistors. Our primary predictions are that Si-based transistors are physically possible without major changes in design philosophy at scales of ∼1 nm wire diameter and ∼3 nm gate length, and that the junctionless transistor [1, 2] may be the only physically sensible design at these length scales. We also present investigations into atomic-level design factors such as dopant positioning and concentration.
Hierarchical simulation of transport in silicon nanowire transistors
Journal of Computational Electronics, 2008
We propose a very fast hierarchical simulator to study the transport properties of silicon nanowire FETs. We obtain the transverse wave functions and the longitudinal effective masses and band-edges of the lowest conduction bands from a nearest-neighbor sp 3 d 5 s * tight-binding study of an infinite nanowire with null external potential. Then we plug these parameters into a self-consistent Poisson-Schrödinger solver, using an effective mass approach and considering the bands decoupled. We apply this method, which gives quantitatively correct results with notable time savings, for the simulation of transport in two different silicon nanowire FETs.