Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices (original) (raw)

A Balanced Ternary Multiplication Circuit Using Recharged Semi-Floating Gate Devices

2006 NORCHIP, 2006

This paper presents a multiplier circuit using Balanced Ternary (BT) Notation. The multiplier can multiply both negative and positive numbers, which is one of the advantage able properties of the balanced ternary numbering systems. By using balanced ternary notation, it is possible to take advantage of carry free multiplication, which is exploited in designing a fast multiplier circuit. The circuit is implemented with Recharged Semi-Floating Gate (RSFG) devices. The circuit operates at 1 GHz clock frequency at a supply voltage of only 1.0 Volt. The circuit is simulated by using Cadence R Analog Design Environment, with CMOS090 process parameters, a 90nm General Purpose Bulk CMOS Process from STMicroelectronics with 7 metal layers.

A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices

Proceedings of The International Symposium on Multiple-Valued Logic

This paper presents a novel voltage mode Balanced Ternary Adder (BTA), implemented with Recharged Semi- Floating Gate Devices. By using balanced ternary notation, it possible to take advantage of carry free addition, which is exploited in designing a fast adder cell. The circuit operates at 1 GHz clock frequency. The supply voltage is only 1.0 Volt. The circuit is simulated by using Cadence R Analog Design Environment, with CMOS090 process parameters, a 90nm General Purpose Bulk CMOS Process from STMicroelectronics with 7 metal layers. All the capacitors are metal plate capacitors, based on vertical coupling capacitance between stacked metal plates.

A novel ternary more, less and equality circuit using recharged semi-floating gate devices

2006 Ieee International Symposium on Circuits and Systems, 2006

This paper presents a novel Ternary More, Less and Equality (MLE) Circuit implemented with Recharged Semi-Floating Gate Transistors. The circuit is a ternary application, and ternary structures may offer the fastest search in a tree structure. The circuit has two ternary inputs, and one ternary output which will be a comparison of the two ternary inputs. The circuit is a useful building block for use in a search tree application. The circuit is simulated by using Cadence R Analog Design Environment with CMOS090 GP process parameters from STMicroelectronics, a 90 nm General Purpose Bulk CMOS Process with 7 metal layers. The circuit operates at a 1 GHz clock frequency. The supply voltage is +/-0.5 Volt. All capacitors are metal plate capacitors, based on a vertical coupling capacitance between stacked metal plates.

Design of Ternary D Flip-Flop Using Neuron MOSFET

In this paper, we have designed D flip-flop using NAND gates. The gates are ternary NAND gates, which are constructed using Neuron MOS transistors. According to D Flip-Flop operation, output will follow the input which is given in the form of ternary logic as 0, 1, 2. A considerable reduction in the number of transistor count is achieved using this new configuration. The circuit simulation is done using T-spice and waveforms are checked using W-edit. The circuit is design using transistor length L=0.18u.

Design and Implementation of Low power Carry Select Adder Using Transmission Gate Logic

Now A days power Reduction techniques play important Role in Low power VLSI Applications. Adder is digital circuit it performing addition operation used in many application like microprocessor and DSP In this paper Low power XOR gate has been designed using transmission gate logic, it is implemented carry select adder for low power VLSI application and compared with CMOS technology. The simulation is performed using a SPICE circuit simulator at 180nm technology node & 1.8V standard CMOS process. Comparison between these techniques has shown a significant power saving to the extent of 60% in case of Transmission gate logic design carry select adder , as compared to CMOS logic in 10-100MHz transition frequency range.

REDUCTION OF WIRING DELAY AND POWER OF AN OPTIMIZED FULL ADDER & HALF ADDER USING MULTI-VALUE LOGIC

The multi value logic based digital circuit is designed by increasing the representation domain from the two level (N=2) switching algebra to N > 2 levels. Universal sets of MVL CMOS gates permit the synthesis and implementation of any MVL digital circuit. The main advantage of this approach is to compensate the inefficiency of existing integrated circuits that are used to implement the universal set of MVL gates. This work deals with: 1) A universal set of IC gates designed and implemented by using CMOS 0.65 μm technology, that carry out extended AND operators: eAND1, eAND2, eAND3, Maximum (MAX) operators and Successor (SUC), to carry out synthesis of any MVL based Multiplexer circuits; and 2) Similarly, a reduced half adder and full adder circuit is designed & implemented by using MVL or quaternary logic. Implemented circuits not just show the exact functionality of the implemented gates and adders but also the feasibility of the MVL combinatorial and memory circuit design. The proposed MVL technique allows designing MVL digital circuit that is set to obtain the values from the binary circuits. Comparison between 65nm and 250nm CMOS technique is performed for full adder, half adder and multiplexer circuits. Also this technique offers low power and small wiring delay, when compared to binary and three value logic. Keywords: MVL logic, successor, full adder using MVL, MVL based half adder and CMOS technology Introduction about Multi-Value Logic (MVL)

Comparative Analysis and Optimization of Active Power and Delay of 1-Bit Full Adder at 45 nm Technology - Satya Prakash Pandey, Raju Gupta and Shyam Akashe (ITM University, Gwalior, INDIA)

IEEE International Conference SESC 2013 organized by MNNIT Allahabad, INDIA, 2013

An overview of performance analysis and compression between various parameters of a low power high speed conventional 1-bit full adder has been presented here. The work elucidated here gives a quantitative comparison of the adder cell performance. This paper shows the advancement over active power, leakage current and delay. The comparative study based on a new logic approach, which reduces power consumption. With power supply of 0.7V, we have achieved reduction in active power consumption of 98.28nW and propagation delay of 0.737ns, which makes this circuit highly energy efficient. In this circuit we have reduced leakage current of 135.9nA. The designs have been carried out by virtuoso tool of cadence at 45nm technology.