CNTFET Full-Adders for Energy-Efficient Arithmetic Applications (original) (raw)
Related papers
Energy Efficient CNTFET Based Full Adder Using Hybrid Logic
International Journal IJRITCC, Priya Kaushal
An applicable high-efficient CNTFET-based full adder cell for practical environments
A low-voltage and energy-efficient full adder cell based on carbon nanotube technology
2010
A Novel Ultra Low-Power 10T CNFET-Based Full Adder Cell Design in 32nm Technology
An Energy-Efficient Full Adder Cell Using CNFET Technology
IEICE Transactions on Electronics, 2012
A low-power high speed full adder cell using carbon nanotube field effect transistors
Ramakrishnareddy Eamani, Indonesian Journal of Electrical Engineering and Computer Science
The Indonesian Journal of Electrical Engineering and Computer Science (IJEECS), 2023
Low‐power consumption ternary full adder based on CNTFET
IET Circuits, Devices & Systems, 2016
Energy-Efficient Ternary Arithmetic Logic Unit Design in CNTFET Technology
Circuits, Systems, and Signal Processing, 2019
Two Efficient Ternary Adder Designs Based On CNFET Technology
Journal of Computer and Knowledge Engineering
Journal of Computer and Knowledge Engineering, 2021
Analysis of FinFET and CNTFET based Hybrid CMOS Full Adder Circuit
IRJET, 2022
Design and Analysis of Low-Power and High Speed Approximate Adders Using CNFETs
Sensors
Performance Investigation of a full adder using CNTFET Technology
Fast and Energy-Efficient CNFET Adders With CDM and Sensitivity-Based Device-Circuit Co-Optimization
Mona Hashemi, Kawsar Haghshenas
2018
Designing High-Speed, Low-Power Full Adder Cells Based on Carbon Nanotube Technology
International Journal of VLSI Design & Communication Systems, 2014
CMOS Full-Adders for Energy-Efficient Arithmetic Applications
High Performance CNFET-based Ternary Full Adders
IETE Journal of Research
14th VLSI Design and Test Symposium (VDAT), 2010
A Novel CNTFET-based Ternary Full Adder
peiman keshavarzian, Rahil Sarikhani
Circuits, Systems, and Signal Processing, 2013
Design and analysis of a novel low-power and energy-efficient 18T hybrid full adder
Microelectronics Journal, 2018
Performance comparison between CNFET & Conventional CMOS based Arithmetic Logic Unit.
International Journal of Engineering Sciences & Research Technology, 2014
Energy Efficient and Process Tolerant Full Adder Design in Near Threshold Region using FinFET
2010
Performance Study of 12-CNTFET and GDI CNTFET based Full Adder in HSPICE
Design and Analysis of a New Carbon Nanotube Full Adder Cell
Journal of Nanomaterials, 2011
IJERT-An Area Efficient Low Power TG Full Adder Design using CMOS Nano Technology
International Journal of Engineering Research and Technology (IJERT), 2014
An Ultra-Low Power Ternary Multi-Digit Adder Applies GDI Method for Binary Operations
Journal of Electrical and Computer Engineering Innovations
2023
Comparative analysis of adiabatic full adder cells in CNFET technology
Engineering Science and Technology, an International Journal, 2016
Electronic System Design …, 2010
Efficient CNTFET-based Ternary Full Adder Cells for Nanoelectronics
Nano-Micro Letters, 2011
Design of Three-valued Logic Based Adder and Multiplier Circuits using Pseudo N-type CNTFETs
IJEER , 2023
IJERT-Power Efficient CMOS Full Adders with Reduced Transistor Count
International Journal of Engineering Research and Technology (IJERT), 2014
A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells
IEEE Access