Power Efficient and High Speed Carry Skip Adder using Binary to Excess One Converter (original) (raw)
Related papers
Arithmetic and Logic Unit (ALU) is a vital component of any CPU. In ALU, adders play a major role not only in addition but also in performing many other basic arithmetic operations like subtraction, multiplication, etc. Thus realizing an efficient adder is required for better performance of an ALU and therefore the processor. For the optimization of speed in adders, the most important factor is carry generation. For the implementation of a fast adder, the generated carry should be driven to the output as fast as possible, thereby reducing the worst path delay which determines the ultimate speed of the digital structure. In conventional carry skip adder the multiplexer is used as a skip logic that provides a better performance and performs an efficient operation with the minimum circuitry. Even though, it affords a significant advantages there may be a large critical path delay revealed by the multiplexer that leads to increase of area usage and power consumption. The basic idea of this paper is to use Binary to Excess-1 Converters (BEC) to achieve lower area and power consumption.
2014
Abstract. The most timing critical part of logic design usually contains one or more arithmetic operations,in which addition is commonly involved. In VLSI applications, area, delay and power are the important factorswhich must be taken into account in the design of a fast adder [1]. The paper attempts to examine the featuresof certain adder circuits which promise superior performance compared to existing circuits. The advantagesof these circuits are low-power consumption, a high degree of regularity and simplicity. The main emphasisis on reducing power consumption in these circuits and also helps in better (power delay product) PDP [3].The carry-skip adder proposed here reduces the time needed to propagate the carry by skipping over groups ofconsecutive adder stages, is known to be comparable in speed to the carry look-ahead technique while it usesless logic area and less power [1]. Carry Skip Adder (CSA) is simulated for different structures such as 2, 4 and8-blocks. Simulation res...
International Journal of Science and Research (IJSR), 2016
The portable equipments such as cellular phones, Personal Digital Assistant (PDA), and notebook personal computer, arise the need of effective circuit area and power efficient VLSI circuits. Addition is the most common and often used arithmetic operation in digital computers and also, it serves as a building block for synthesis all other arithmetic operations. Low-power and high-speed adder cells (like carry skip adder) are used in battery operation based devices. Now the biggest challenge is reduction of adder power consumption and delay while maintaining the high performance in different types of circuit design. In conventional carry skip adder the multiplexer is used as a skip logic that provides a better performance and performs an efficient operation with the minimum circuitry. Even though, it affords a significant advantages there may be a large critical path delay revealed by the multiplexer and also it containing twelve transistors that leads to increase of area usage and power consumption. The proposed method uses compound gates such as AOI and OAI as skip logic in the design that leads to decrease area usage, delay and power consumption, also in addition the parallel prefix adder is included to attain further reduction of power. The design is coded in VHDL and simulated in ModelSim and its area, delay and power are analyzed using Xilinx_ISE 9.2i.
Design of High-Speed and Low Power Carry Skip Adder
In this paper we present high speed 8-bit Carry Skip Adder (CSA) compared with Ripple Carry Adder (RAC) and conventional Carry Skip Adder (CSA). This is more efficient in terms of power consumption, area usage and speed. Instead to make multiplexer logic, the propose architecture made of AND-OR-Inverter (AIO) combination gate for carry skip adder. The propose architecture are evaluated by comparing their speed, power and area with those of other address using 180nm, 90nm and 45nm static CMOS technology.
Design of Low Power, Area-Efficient Carry Select Adder
Design of low power and area-efficient logic systems forms an integral part and largest areas of research in the field of VLSI Design. Addition is the most fundamental arithmetic operation. In this paper, a low power, area-efficient carry select adder is proposed. CSA is one of the fastest adders used in dataprocessing systems to perform fast arithmetic operation. Secondly, structure of carry select adder is such that there is scope of reducing the area and power consumption. Thirdly, there is scope to reduce the area by using some add-one scheme. So, a Modified Carry Select Adder(MCSA) is designed by using single Ripple Carry Adder(RCA) and Binary to Excess-1 Converter (BEC) instead of dual RCAs in order to reduce the area and power consumption with small speed penalty. CSA and MCSA structures are designed for 8-bit, 16-bit, 32bit and 64-bit. Result analysis shows that MCSA is better than CSA.
IJERT-Design of Low Power, Area-Efficient Carry Select Adder
International Journal of Engineering Research and Technology (IJERT), 2013
https://www.ijert.org/design-of-low-power-area-efficient-carry-select-adder https://www.ijert.org/research/design-of-low-power-area-efficient-carry-select-adder-IJERTV2IS101008.pdf Design of low power and area-efficient logic systems forms an integral part and largest areas of research in the field of VLSI Design. Addition is the most fundamental arithmetic operation. In this paper, a low power, area-efficient carry select adder is proposed. CSA is one of the fastest adders used in dataprocessing systems to perform fast arithmetic operation. Secondly, structure of carry select adder is such that there is scope of reducing the area and power consumption. Thirdly, there is scope to reduce the area by using some add-one scheme. So, a Modified Carry Select Adder(MCSA) is designed by using single Ripple Carry Adder(RCA) and Binary to Excess-1 Converter (BEC) instead of dual RCAs in order to reduce the area and power consumption with small speed penalty. CSA and MCSA structures are designed for 8-bit, 16-bit, 32bit and 64-bit. Result analysis shows that MCSA is better than CSA.
IJERT-Low-Power and Area-Efficient Carry Select Adder
International Journal of Engineering Research and Technology (IJERT), 2013
https://www.ijert.org/low-power-and-area-efficient-carry-select-adder https://www.ijert.org/research/low-power-and-area-efficient-carry-select-adder-IJERTV2IS120617.pdf Design of power-efficient and high-speed data path logic systems are one of the most substantial areas of research in VLSI system design. In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position has been summed and a carry propagated into the next position. The CSLA is used in many computational systems to alleviate the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum. However, the CSLA is not area efficient because it uses multiple pairs of Ripple Carry Adders (RCA) to generate partial sum and carry by considering carry input, then the final sum and carry are selected by the multiplexers (mux). The basic idea of this work is to use Binary to Excess-1 Converter (BEC) instead of RCA in the regular CSLA to achieve high speed and low power consumption.
PERFORMANCE AND ANALYSIS OF LOW POWER, AREAEFFICIENT AND HIGH SPEED CARRYFAST ADDER
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8, 16,32,and 64-bit square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power. Binary to Excess-1 Converter (BEC) instead of RCA with the regular CSLA to achieve lower area and power consumption. The main advantage of this BEC logic comes from the lesser number of logic gates than the n-bit Full Adder structure. The delay and area evaluation methodology of the basic adder blocks. The SQRT CSLA has been chosen for comparison with the proposed design as it has a more balanced delay, and requires lower power and area. Reducing the area and power consumption in the CSLA. Efficient gate-level modification to significantly reduce the area and powerof the CSLA.
Low power and Area Efficient Carry Select Adder
sittechno.org
Design of power-efficient and highspeed data path logic systems are one of the most substantial areas of research in VLSI system design. In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position has been summed and a carry propagated into the next position. The CSLA is used in many computational systems to alleviate the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum. However, the CSLA is not area efficient because it uses multiple pairs of Ripple Carry Adders (RCA) to generate partial sum and carry by considering carry input, then the final sum and carry are selected by the multiplexers (mux). The basic idea of this work is to use Binary to Excess-1 Converter (BEC) instead of RCA in the regular CSLA to achieve high speed and low power consumption.
Design and Implementation of Different types of Carry skip adder
IRJET, 2022
In many computer systems, adders are the basic building blocks. The Carry-Skip Adder (CSA) is one of the fastest and most space-effective adder topologies. The existing CSA structure available in the literature is high because of its conventional design. In the proposed adder, compound gates are employed. Performance improvement is observed due to the presence of AOI and OAI logic. 8-bit CSA is designed and analyzed using both Xilinx ISE 14.2 Vivado Design Suite and Cadence, to analyze area and power. The design is implemented on a Zed board using Verilog HDL programming.