Low power and Area Efficient Carry Select Adder (original) (raw)
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IJERT-Low-Power and Area-Efficient Carry Select Adder
International Journal of Engineering Research and Technology (IJERT), 2013
https://www.ijert.org/low-power-and-area-efficient-carry-select-adder https://www.ijert.org/research/low-power-and-area-efficient-carry-select-adder-IJERTV2IS120617.pdf Design of power-efficient and high-speed data path logic systems are one of the most substantial areas of research in VLSI system design. In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position has been summed and a carry propagated into the next position. The CSLA is used in many computational systems to alleviate the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum. However, the CSLA is not area efficient because it uses multiple pairs of Ripple Carry Adders (RCA) to generate partial sum and carry by considering carry input, then the final sum and carry are selected by the multiplexers (mux). The basic idea of this work is to use Binary to Excess-1 Converter (BEC) instead of RCA in the regular CSLA to achieve high speed and low power consumption.
Power Efficient and High Speed Carry Skip Adder using Binary to Excess One Converter
— The design of high-speed and low-power VLSI architectures need efficient arithmetic processing units, which are optimized for the performance parameters, namely, speed and power consumption. Adders are the key components in general purpose microprocessors and digital signal processors. As a result, it is very pertinent that its performance augers well for their speed performance. Additionally, the area is an essential factor which is to be taken into account in the design of fast adders. Towards this end, high-speed, low power and area efficient addition and multiplication have always been a fundamental requirement of high-performance processors and systems. The major speed limitation of adders arises from the huge carry propagation delay encountered in the conventional adder circuits, such as ripple carry adder and carry save adder. Observing that a carry may skip any addition stages on certain addend and augend bit values, researchers developed the carry-skip technique to speed up addition in the carry-ripple adder. Using a multilevel structure, carry-skip logic determines whether a carry entering one block may skip the next group of blocks. Because multilevel skip logic introduces longer delays, Therefore, in this paper we examine The basic idea of this work is to use Binary to Excess-1 converter (BEC) instead of RCA with Cin=1 in conventional CSkA in order to reduce the area and power. BEC uses less number of logic gates than N-bit full adder.
Design of Low Power, Area-Efficient Carry Select Adder
Design of low power and area-efficient logic systems forms an integral part and largest areas of research in the field of VLSI Design. Addition is the most fundamental arithmetic operation. In this paper, a low power, area-efficient carry select adder is proposed. CSA is one of the fastest adders used in dataprocessing systems to perform fast arithmetic operation. Secondly, structure of carry select adder is such that there is scope of reducing the area and power consumption. Thirdly, there is scope to reduce the area by using some add-one scheme. So, a Modified Carry Select Adder(MCSA) is designed by using single Ripple Carry Adder(RCA) and Binary to Excess-1 Converter (BEC) instead of dual RCAs in order to reduce the area and power consumption with small speed penalty. CSA and MCSA structures are designed for 8-bit, 16-bit, 32bit and 64-bit. Result analysis shows that MCSA is better than CSA.
IJERT-Design of Low Power, Area-Efficient Carry Select Adder
International Journal of Engineering Research and Technology (IJERT), 2013
https://www.ijert.org/design-of-low-power-area-efficient-carry-select-adder https://www.ijert.org/research/design-of-low-power-area-efficient-carry-select-adder-IJERTV2IS101008.pdf Design of low power and area-efficient logic systems forms an integral part and largest areas of research in the field of VLSI Design. Addition is the most fundamental arithmetic operation. In this paper, a low power, area-efficient carry select adder is proposed. CSA is one of the fastest adders used in dataprocessing systems to perform fast arithmetic operation. Secondly, structure of carry select adder is such that there is scope of reducing the area and power consumption. Thirdly, there is scope to reduce the area by using some add-one scheme. So, a Modified Carry Select Adder(MCSA) is designed by using single Ripple Carry Adder(RCA) and Binary to Excess-1 Converter (BEC) instead of dual RCAs in order to reduce the area and power consumption with small speed penalty. CSA and MCSA structures are designed for 8-bit, 16-bit, 32bit and 64-bit. Result analysis shows that MCSA is better than CSA.
IMPLEMENTATION OF LOW-POWER AND AREA-EFFICIENT 64BIT CARRY SELECT ADDER
Now a day’s hottest area of research in VLSI system is design of the area, high-speed and power-efficient data path logic systems. All processor consisting of Arithmetic & logical Unit (ALU) and adder plays an important role for design of ALU. In digital adders, the speed of addition is limited by the time required to send a carry through the adder. Carry Select Adder (CSLA) is an efficient is used for data-processing processors to perform fast arithmetic functions. The proposed work reduces area and power consumption to a great extent with the help of a simple ripple carry adder (RCA) and gate-level architecture. Regular CSLA consist of two RCA and proposed design has been projected by single RCA. This improves the performance of the proposed designs then the regular designs in terms of power consumption and area.
An Efficient Carry Select Adder with Less Delay and Reduced Area Application
Design of area, high speed and power-efficient data path logic systems forms the largest areas of research in VLSI system design. The addition speed is limited by the time necessary to transmit a carry through the adder. Carry Select Adder (CSLA) is one of the fastest adders used in several dataprocessing processors to perform fast arithmetic purpose. From the configuration of the CSLA, it is clear that there is scope for decreasing the area and delay in the CSLA. This work uses a simple and an efficient gate-level modification which drastically reduces the area and delay of the CSLA. Based on this modification 16, 32, 64 and 128-bit square-root Carry Select Adder (SQRT CSLA) architectures have been improved and compared with the regular SQRT CSLA architecture. The proposed design has compact area and delay to a great extent when compared with the regular SQRT CSLA. This work estimates the performance of the planned designs with the regular designs in terms of delay, area and synthesis are implemented in Xilinx FPGA. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.
PERFORMANCE AND ANALYSIS OF LOW POWER, AREAEFFICIENT AND HIGH SPEED CARRYFAST ADDER
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8, 16,32,and 64-bit square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power. Binary to Excess-1 Converter (BEC) instead of RCA with the regular CSLA to achieve lower area and power consumption. The main advantage of this BEC logic comes from the lesser number of logic gates than the n-bit Full Adder structure. The delay and area evaluation methodology of the basic adder blocks. The SQRT CSLA has been chosen for comparison with the proposed design as it has a more balanced delay, and requires lower power and area. Reducing the area and power consumption in the CSLA. Efficient gate-level modification to significantly reduce the area and powerof the CSLA.
Arithmetic and Logic Unit (ALU) is a vital component of any CPU. In ALU, adders play a major role not only in addition but also in performing many other basic arithmetic operations like subtraction, multiplication, etc. Thus realizing an efficient adder is required for better performance of an ALU and therefore the processor. For the optimization of speed in adders, the most important factor is carry generation. For the implementation of a fast adder, the generated carry should be driven to the output as fast as possible, thereby reducing the worst path delay which determines the ultimate speed of the digital structure. In conventional carry skip adder the multiplexer is used as a skip logic that provides a better performance and performs an efficient operation with the minimum circuitry. Even though, it affords a significant advantages there may be a large critical path delay revealed by the multiplexer that leads to increase of area usage and power consumption. The basic idea of this paper is to use Binary to Excess-1 Converters (BEC) to achieve lower area and power consumption.
High Speed, Low Power, Area Efficient Mux-Add and Bec Based Implementation of Carry Select Adder
Adder being the basic hardware block of any arithmetic operation, the major constraint in the field of signal processors, data processors to perform any operations are highly dependent on the adder performance of the circuit. The gate level implementation of the carry select adder (CSLA) and modified carry select adder has significantly reduced the area and power consumption which replaced the ripple carry adder (RCA) used in modified CSLA with MUX-ADD block has further reduced the power consumption by efficiently utilizing the area with faster performance.
A Novel Design of Low Power High Speed Carry Select Adder
Carry Select Adder (CSLA) is one of the fastest adders used in many computational systems to perform fast arithmetic operations. It performs n-bit addition and provides a sum of n+1 bit. The structure of CSLA gives the future scope of reducing the area and power consumption which are needed for the rapidly growing mobile industry. The modified 64-Bit CSLA architecture has developed using Binary to Excess-1 converter(BEC).This paper proposes an efficient method of replacing RCA in regular proposal with BEC in modified proposal.