KEEPER DESIGNS FOR WIDE FAN IN DYNAMIC LOGIC (original) (raw)
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A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates
Proceedings of the 43rd annual conference on Design automation - DAC '06, 2006
Substantial increase in leakage current and threshold voltage fluctuations are making design of robust wide fan-in dynamic gates a challenging task. Traditionally, a PMOS keeper transistor has been employed to compensate for leakage current of pull down (NMOS) network. However, to maintain acceptable noise margin level in sub-100 nm technologies, large PMOS is necessary, which results in substantial contention (during pull down) and severe loss of performance. In this paper, a novel keeper architecture is proposed which is capable of significantly reducing the contention and improving the performance and power consumption. Using circuit simulations, superior characteristics of the proposed keeper is demonstrated in comparison to those of the traditional as well as state-of-the-art keepers. It is shown that for an 8-input OR gate, in presence of 15% V th fluctuations, the proposed architecture can lead to 20%, 15%, and more than 40% reduction in power consumption, mean delay, and standard deviation of delay, respectively, when compared to traditional keeper circuit. Categories and Subject Descriptors B.7.1 [Integrated Circuits]: Types and Design Styles-VLSI (very large scale integration).
Low power and high performance circuit techniques for high fan-in dynamic gates
SCS 2003. International Symposium on Signals, Circuits and Systems. Proceedings (Cat. No.03EX720), 2004
Domino keeper has to be upsized to keep the noise margin in high fan-in dynamic gates, which increases the power consumption and slows down the evaluation. We propose a four-phase non-full swing keeper design to solve this dilemma. Non-full swing switching at the keeper gate together with alleviated contention help to reduce power consumption and delay. Simulation of 16-input OR gate using 0.13um CMOS SPICE parameters shows that proposed keeper design can reduce power consumption and delay by 26% and 24%, respectively.
Speeding-up wide-fan in domino logic using a controlled strong PMOS keeper
2008 International Conference on Computer and Communication Engineering, 2008
Wide fan in domino logic finds a variety of applications in microprocessors, digital signal processors, and dynamic memory. Specifically, there is a large number of applications that contain 8 or more transistors connected in parallel in the pull-down network (PDN) and thus the subthreshold leakage and charge sharing become severe. So, a strong PMOS keeper must be used in order to compensate for this leakage. However, the use of a strong keeper in the conventional domino circuit degrades the speed of the circuit considerably or results in an erroneous output. In this paper, a novel technique that acts to speed up the operation of wide fan in domino logic using a properly sized keeper is proposed. The keeper is controlled via a controlling CMOS circuit. Some design issues of this technique such as the effect of the charge sharing on the operation of the proposed circuit and the size of the PMOS keeper will be discussed in this paper. Simulation will be carried out for the 0.13 µm technology with V DD =1.2 V for the case of 16 NMOS transistors in the PDN. Simulation results show the better noise immunity of the proposed circuit and the larger speed, however at the cost of increasing the area.
Robust low leakage controlled keeper by current-comparison domino for wide fan-in gates
Integration, 2012
In this paper, a new design for low leakage and noise immune wide fan-in domino circuits is presented. The proposed technique uses the difference and the comparison between the leakage current of the OFF transistors and the switching current of the ON transistors of the pull down network to control the PMOS keeper transistor, yielding reduction of the contention between keeper transistor and the pull down network from which previously proposed techniques have suffered. Moreover, using the stacking effect, leakage current is reduced and the performance of the current mirror is improved. Results of simulation in high performance 16 nm predictive technology model (PTM) demonstrate that the proposed circuit exhibits about 39% less power consumption, and nearly 2.57 times improvement in noise immunity with a 41% die area overhead for a 64-bit OR gate compared to a standard domino circuit.
IJERT-Robust Low Leakage Controlled Keeper by Current Comparison Domino for Wide Fan in Gates
International Journal of Engineering Research and Technology (IJERT), 2013
https://www.ijert.org/robust-low-leakage-controlled-keeper-by-current-comparison-domino-for-wide-fan-in-gates https://www.ijert.org/research/robust-low-leakage-controlled-keeper-by-current-comparison-domino-for-wide-fan-in-gates-IJERTV2IS120324.pdf A new design for low leakage and noise immune wide fan-in domino circuits is presented. The proposed technique uses the between the leakage current the OFF transistors and the switching current of the ON transistors of the pull down network to control the PMOS keeper transistor, yielding reduction of the contention between keeper transistor and the pull down network from which previously proposed, techniques have suffered. Moreover, using the stacking effect leakage current is reduced and the performance of the current mirror is improved. Results of simulation in high performance 16nm predictive technology model(PTM)demonstrate that the proposed circuit exhibits about 39% less power consumption, and nearly 2.57 times improvement in noise immunity with a 41% die area overhead for a 64-bit OR gate compared to a standard domino circuit. Substantial increase in leakage current and threshold voltage fluctuations are making design of robust wide fan-in dynamic gates a challenging task. Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. Domino logic circuits with high fan-in are widely used due to their high performance. Scaling down the supply voltage is known to be the most effective way to reduce power consumption. For lower power supply voltage, the threshold voltage of transistors also needs to be scaled down to meet performance requirements. However, the lowering of the threshold voltage leads to an exponential growth of sub threshold leakage current. pull down network (PDN), even when all the inputs are at the low logic level. This leakage is due to the BTBT (band-to-band-tunneling) current, gate tunneling current and the sub threshold current. In addition, voltages of dynamic nodes degrade to zero due to charges haring in the PDN yielding insufficient noise immunity. Use of NMOS transistors in the PDN with relatively high Vth has been proposed as a solution. However, increasing Vth increases the delay of discharging the dynamic node. Another proposed solutions to use a PMOS keeper. However, there is a speed degradation and power loss due to the contention between the pull down network and the strong keeper. Thus, performance of wide dynamic gates is affected by both sub threshold leakage and noise sources. 2 LITERATURE REVIEW Several domino circuits have been proposed in the literature such as HS domino, Split Domino, CKCCD Domino, CKD Domino etc. The main goal of these circuit design techniques is improved noise immunity and circuit performance, especially in wide fan-in circuit.
Noise-Tolerant XOR-Based Conditional Keeper for High Fan-in Dynamic Circuits
2005 IEEE International Symposium on Circuits and Systems
Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits is presented in this paper. Noise immunity is enhanced by conditionally turning on the conditional keepers. The conditional keeper is turned off at some critical moments to reduce the delay and power consumption. The timing of control signals and their effects on noise immunity, power and delay are also examined. High fanin dynamic circuits are used to demonstrate the effectiveness of the conditional keeper on noise immunity. Distributed power gating combined with clock gating design is also examined. All the simulation results are based on TSMC 100nm CMOS technology. Compared to conventional techniques, under the same unity-gain DC noise criteria, more than 20% power reduction and 20% delay reduction are achieved. Under the same delay criteria, more than 1.25X noise immunity improvement is attained. I.
High speed wide fan‐in designs using clock controlled dual keeper domino logic circuits
ETRI Journal
Clock Controlled Dual keeper Domino logic structures (CCDD_1 and CCDD_2) for achieving a high-speed performance with low power consumption and a good noise margin are proposed in this paper. The keeper control circuit comprises an additional PMOS keeper transistor controlled by the clock and foot node voltage. This control mechanism offers abrupt conditional control of the keeper circuit and reduces the contention current, leading to high-speed performance. The keeper transistor arrangement also reduces the loop gain associated with the feedback circuitry. Hence, the circuits offer less delay variability. The design and simulation of various wide fan-in designs using 180 nm CMOS technology validates the proposed CCDD_1 and CCDD_2 designs, offering an increased speed performance of 7.2% and 8.5%, respectively, over a conventional domino logic structure. The noise gain margin analysis proves good robustness of the CCDD structures when compared with a conventional domino logic circuit configuration. A Monte Carlo simulation for 2,000 runs under statistical process variations demonstrates that the proposed CCDD circuits offer a significantly reduced delay variability factor.
2013 IEEE CONFERENCE ON INFORMATION AND COMMUNICATION TECHNOLOGIES, 2013
Domino CMOS logic circuits are widely used these days in the design of high-performance modules in modern day integrated chips and microprocessors. The feature of high speed and less area overhead of these logic circuits compared to other logic styles make them a popular choice in the design of high speed circuits. As power consumption is directly proportional to the dynamic node capacitance, a new circuit technique is presented in this paper which employs the partitioning of dynamic node capacitance with the help of a splitter transistor to reduce the power consumption. With the help of a modified keeper circuitry, the contention between keeper and the pull down evaluation network is reduced drastically. Simulation results show a reduction of 78.91 % when compared to the Conditional Keeper (CKP) technique and reduction by 65.51 % when compared with the Adaptive Pseudo Dual Keeper (APDK) scheme. The reduction is about 83.56 % when compared to CKP and 70.27 % when pitted against the APDK when the issue of contention current is taken up. The reduction in power and contention current is found to be true when the design concept was tested for a 32 bit comparator circuitry. Simulations have been performed using the SILVACO EDA tool on a 32-bit wide fan-in OR gate in 32nm process technology at a frequency of 1.5 GHz and supply voltage of 0.9V. Monte Carlo simulations have also been performed to test an idea which makes the circuit tolerant to process variations.
IJERT-Leakage Tolerance High Performance Wide Fan-In Domino Logic Circuit Design
International Journal of Engineering Research and Technology (IJERT), 2012
https://www.ijert.org/leakage-tolerance-high-performance-wide-fan-in-domino-logic-circuit-design https://www.ijert.org/research/leakage-tolerance-high-performance-wide-fan-in-domino-logic-circuit-design-IJERTV1IS9326.pdf Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose domino logic circuit techniques to improve the robustness and performance along with leakage power. In this paper a new high performance low power and noise tolerant circuit technique for wide fan-in domino logic is proposed where feedback is done from the output of CMOS inverter to the gate of footer transistor. In this domino circuit a chain of evaluation network uses well known stacking effect technique to reduce the leakage. The leakage current is also decreased by exploiting the footer transistor in diode configuration, which results in increased noise immunity. Simulation results of wide fan-in gates designed using a 65-nm high-performance predictive technology model demonstrate 51% power reduction and at least 2.41× noise-immunity improvement at the same delay compared to the standard domino circuits for 8-bit OR gates.
A survey on different keeper design topologies for high speed wide AND-OR domino circuits
2012
In this paper, we analyze and compare different keeper design topologies for lowering the active mode power consumption, increasing the speed, enhancing the noise immunity and reducing the subthreshold leakage energy of domino logic circuits. This work briefly surveys domino keeper techniques for high fan-in domino circuits. We compared the power, delay, process tracking and VDD tracking of different topologies. These topologies have been prototyped in 130nm CMOS technology at 125°C temperature. The simulation results reveal that conditional keeper technique gives the better results in terms of reduction in delay, power consumption whereas Leakage current replica (LCR) based keeper shows superior performance in terms of noise overhead, process variation and VDD tracking as compared to other alternatives keepers. As compare to conventional circuit, conditional keeper gives 55% reduction in delay as well as 15% reduction in power while leakage current replica (LCR) gives 95% reduction in noise overhead and providing capability of process and VDD tracking.