Area Efficient Turbo Encoder for Wireless Applications on FPGA (original) (raw)
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Turbo encoder and decoder chip design and FPGA device analysis for communication system
International Journal of Reconfigurable and Embedded Systems (IJRES), 2023
Turbo codes are error-correcting codes with performance that is close to the Shannon theoretical limit (SHA). The motivation for using turbo codes is that the codes are an appealing mix of a random appearance on the channel and a physically realizable decoding structure. The communication systems have the problem of latency, fast switching, and reliable data transfer. The objective of the research paper is to design and turbo encoder and decoder hardware chip and analyze its performance. Two convolutional codes are concatenated concurrently and detached by an interleaver or permuter in the turbo encoder. The expected data from the channel is interpreted iteratively using the two related decoders. The soft (probabilistic) data about an individual bit of the decoded structure is passed in each cycle from one elementary decoder to the next, and this information is updated regularly. The performance of the chip is also verified using the maximum a posteriori (MAP) method in the decoder chip. The performance of field-programmable gate array (FPGA) hardware is evaluated using hardware and timing parameters extracted from Xilinx ISE 14.7. The parallel concatenation offers a better global rate for the same component code performance, and reduced delay, low hardware complexity, and higher frequency support.
Re-configurable Optimized Area Turbo Decoder for Wireless Applications
IOSR Journal of Electronics and Communication Engineering, 2014
Today, the wireless communication is an emanating requirement of day to day process. Due to the noisy environment in wireless communication there is a need of coding system, which can provide high data rate with error free communication. The turbo codes also known as Parallel Convolutional Concatenated Code (PCCC) provides high data rate with bit error rate performance improvement in communication system. With the advent demand of miniaturization, an area efficient turbo decoder of constraint length 3 is proposed in this paper. The turbo decoder used a single SISO (Soft Input Soft Output) decoder architecture in this paper to reduce the area consumption. The SOVA (Soft Output Viterbi Algorithm) is used as a decoding algorithm in SISO decoders. It is based on two step algorithm. The proposed design is simulated using Matlab and synthesized on Xilinx Virtex-2p (xc2vp30-ff896-5) FPGA. The performance of proposed Turbo decoder will be compared for FPGAs in terms of number of slice Flip-flops, LUTs and frequency. The Synthesis results show a 3% improvement in the utilized no. of slice flip-flop and 49% improvement in terms of frequency.
FPGA Based Area Efficient Turbo Decoder For Wireless Communication
2013
To fulfil the extensive need of high data rate transfer in today’s wireless communication systems such as WiMAX and 4G LTE (Long Term Evolution), the turbo codes gives an exceptional performance. They have allowed for near Shannon limit information transfer in modern communication systems. As the performance of these codes increases, their decoding complexity is also increases and so the power consumption. To reduce this complexity without decreasing its BER (Bit Error Rate) performance a novel modification over SOVA (Soft output Viterbi Algorithm) is proposed in this paper. The proposed model is also implemented on FPGA Xilinx Virtex 5 XC5VLX85ff676-2. The simulation results over MATLAB has been shown, indicates a comparable BER as compared to LOG-MAP with reduced complexity. The synthesis results over Xilinx FPGA shows an improvement of 12% over area utilization as compared to MAX-LOG-MAP implementation. So with reduced area and low BER, a cost effective solution proposed in this ...
Design and Implementation of a Turbo Code System on FPGA
— Error control coding is an important part of communications systems to recover original transmitted data in fading environments. In 3G and 3G beyond mobile systems, Turbo code technology has been used because of its outperformance compared to the other technologies. The contributions of the paper are to study the Turbo code, simulate its on Matlab, then design and implement the code on FPGA successfully.
FPGA Performance Analysis of LDPC and Turbo Codes for Communication System
Research Square (Research Square), 2022
The wireless communication system is based on several coding schemes such as turbo codes, LDPC codes, convolutional, polar, and systematic, etc. The coding techniques should satisfy the hardware system requirements while machine and device communication is taken place. The turbo codes provide a good coding gain close to Shannon's limit, whereas LDPC codes have the ability to provide error corrected data over a noisy channel. The research article presents the comparative performance analysis of turbo and LDPC coding hardware architecture. The encoder and decoder hardware chip of turbo and LDPC is designed using Xilinix ISE 14.7 software, targeted Virtex-5 FPGA. The performance of both coding methods is evaluated using iterative coding scheme. The FPGA hardware complexity is analyzed in terms of hardware and FPGA performance parameters such as slices, flip flops, LUTs and IoBs utilization. The performance the coding methods are also analyzed in terms of timing information related parameters such as path delay, minimum duration, minimum and maximum time of the clock signal, etc. The research work is very much helpful for 4G and 5G mobile communication requirements in device to device communication.
An FPGA realization of simplified turbo decoder architecture
International Journal of Physical Sciences, 2011
The key issue of applying Turbo codes is to find an efficient implementation of turbo decoder. This paper addresses the implementation of a simplified and efficient turbo decoder in field programmable gate array (FPGA) technology. A simplified and efficient implementation of a Turbo decoder with minor performance loss has been proposed. An integer Turbo decoder based on the standard 2's complement number system after considering the issues of dynamic range, truncation effect and other algorithm related subjects has been introduced. The efficient implementation comes from algorithm modification, integer arithmetic and compact hardware management. Based on the Max-Log-MAP decoding algorithm, the branch metric is modified by weighting a priori value, resulting in a significant BER improvement. The Turbo decoder takes in 8-level integer inputs generates 7-bit soft-decisions and calculates all metrics on integers, avoiding complex floating point or fixed-point arithmetic. By manipulating memory address, delay associated with interleaving and de-interleaving is eliminated, resulting in much higher throughput. Also, by taking advantage of identical decoder function, Turbo decoder is implemented in a single-decoder structure, making efficient use of memory and logic cells.
A Parallel turbo encoder-decoder scheme
The field of forward error correction was greatly influenced by the discovery of turbo codes. This invention led to a great improvement in terms of Bit-Error-Rate (BER). Various schemes have been proposed and are based either on parallel or serial designs of concatenated decoders. These decoders are iterative using SOVA (soft output viterbi) or MAP (maximum a posteriori) algorithms. They introduce superior recovery functions of data which have been transmitted through noisy environments. Actually, these turbo schemes compared to convolutional codes achieve better data recovery with the increase of the constraint length. Considering all previous principles, we designed a new parallel turbo encoder-decoder system. This system was compared to already existing serial and parallel turbo coding schemes and to a convolutional encoder. Performance level was verified through simulations including Additive White Guassian noise. BER analysis exhibited better results compared to all other designs for various numbers of iterations.
Implementation and performance of parallellised turbo decoders
IET Communications, 2011
In this study, the authors discuss the implementation of a low latency decoding algorithm for turbo codes and repeat accumulate codes and compare the implementation results in terms of maximum available clock speed, resource consumption, error correction performance and the data (information bit) rate. In order to decrease the latency a parallellised decoder structure is introduced for these mentioned codes and the results are obtained by implementing the decoders on a field programmable gate array. The memory collision problem is avoided by using collision-free interleavers. Through a proposed quantisation scheme and normalisation in forward/backward recursions, computational issues are handled for overcoming the overflow and underflow issues in a fixed point arithmetic. Also, the effect of different implementation styles are observed.
Design of Error Correction and Allusion in Turbo Decoder for Wireless Application - EICA176
Wireless sensor network (WSN) consists of limited energy resources, which reduce the processing capabilities and a radio frequency communication unit with limited transmission power. In wireless communication, Automatic Repeat request (ARQ) technique are used which has power loss in packet retransmission. Then Error correcting code(ECC) can be used to reduce the number of packet retransmission Turbo codes are error correcting codes with at least two dimensions (i.e. each datum is encoded at least twice).The decoding of turbo codes is based on an iterative procedure using the concept of extrinsic information. Highly parallel decoders for convolution turbo codes have been studied by proposing two parallel decoding architectures and a design approach of parallel interleaves. This paper analysis the parallel concatenation turbo encoder and error correction circuit. It detects the error in a given data, if the data should have error then it intimate the error to the user and recover that error.
Design and Implementation Different Types of Turbo Decoder with Various Parameters
International Journal of Computer Applications, 2017
This paper presents design and implementation of turbo code, after that many types of decoders are introduced with various many parameters such as(number of iteration, length of code, number of frame, type of decoding techniques, rate, generator polynomial and type of channel) get the Bit Error Rate (BER) for each case, and compare the results. This work in order to study the effect of each parameter on the performance of Turbo Code to specify the parameters that give the optimum performance of this codes. Finally turbo encoder implemented on FPGA device.