Re-configurable Optimized Area Turbo Decoder for Wireless Applications (original) (raw)
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FPGA Based Area Efficient Turbo Decoder For Wireless Communication
2013
To fulfil the extensive need of high data rate transfer in today’s wireless communication systems such as WiMAX and 4G LTE (Long Term Evolution), the turbo codes gives an exceptional performance. They have allowed for near Shannon limit information transfer in modern communication systems. As the performance of these codes increases, their decoding complexity is also increases and so the power consumption. To reduce this complexity without decreasing its BER (Bit Error Rate) performance a novel modification over SOVA (Soft output Viterbi Algorithm) is proposed in this paper. The proposed model is also implemented on FPGA Xilinx Virtex 5 XC5VLX85ff676-2. The simulation results over MATLAB has been shown, indicates a comparable BER as compared to LOG-MAP with reduced complexity. The synthesis results over Xilinx FPGA shows an improvement of 12% over area utilization as compared to MAX-LOG-MAP implementation. So with reduced area and low BER, a cost effective solution proposed in this ...
Area Efficient Turbo Encoder for Wireless Applications on FPGA
Error control is the major insistence in today's wireless communication systems. In this era parallel concatenated convolutional codes known as turbo codes plays a crucial role. These codes have been chosen as error control approach for various wireless applications such as UMTS (Universal Mobile Telecommunication System),DVB (Digital Video Broadcasting) etc. In this paper an area efficient turbo encoder (2, 1, 3) is proposed to suffice the elevated demand of miniaturization in future wireless communication. The proposed design is simulated using matlab and synthesized on Xilinx Virtex-2p (xc2vp30-ff896-5) FPGA. During simulation the proposed design is compared with the matlab model of RSC encoder. The performance of proposed Turbo encoder will be compared for FPGAs in terms of number of slices, number of slice Flip-flops and the number of registers. The Synthesis results show a 7% improvement in the utilized no. of slices and slice flip-flop. So an area efficient, cost effective Parallel Concatenated Convolutional Code Encoder has been proposed in this paper.
An FPGA realization of simplified turbo decoder architecture
International Journal of Physical Sciences, 2011
The key issue of applying Turbo codes is to find an efficient implementation of turbo decoder. This paper addresses the implementation of a simplified and efficient turbo decoder in field programmable gate array (FPGA) technology. A simplified and efficient implementation of a Turbo decoder with minor performance loss has been proposed. An integer Turbo decoder based on the standard 2's complement number system after considering the issues of dynamic range, truncation effect and other algorithm related subjects has been introduced. The efficient implementation comes from algorithm modification, integer arithmetic and compact hardware management. Based on the Max-Log-MAP decoding algorithm, the branch metric is modified by weighting a priori value, resulting in a significant BER improvement. The Turbo decoder takes in 8-level integer inputs generates 7-bit soft-decisions and calculates all metrics on integers, avoiding complex floating point or fixed-point arithmetic. By manipulating memory address, delay associated with interleaving and de-interleaving is eliminated, resulting in much higher throughput. Also, by taking advantage of identical decoder function, Turbo decoder is implemented in a single-decoder structure, making efficient use of memory and logic cells.
Turbo encoder and decoder chip design and FPGA device analysis for communication system
International Journal of Reconfigurable and Embedded Systems (IJRES), 2023
Turbo codes are error-correcting codes with performance that is close to the Shannon theoretical limit (SHA). The motivation for using turbo codes is that the codes are an appealing mix of a random appearance on the channel and a physically realizable decoding structure. The communication systems have the problem of latency, fast switching, and reliable data transfer. The objective of the research paper is to design and turbo encoder and decoder hardware chip and analyze its performance. Two convolutional codes are concatenated concurrently and detached by an interleaver or permuter in the turbo encoder. The expected data from the channel is interpreted iteratively using the two related decoders. The soft (probabilistic) data about an individual bit of the decoded structure is passed in each cycle from one elementary decoder to the next, and this information is updated regularly. The performance of the chip is also verified using the maximum a posteriori (MAP) method in the decoder chip. The performance of field-programmable gate array (FPGA) hardware is evaluated using hardware and timing parameters extracted from Xilinx ISE 14.7. The parallel concatenation offers a better global rate for the same component code performance, and reduced delay, low hardware complexity, and higher frequency support.
A Concept Paper on‘Complexity and Performance Trade-offs of SISO Turbo Decoders’
Turbo codes are the best coding scheme for error correction in high-speed wireless systems because they achieve the highest coding gain. However, the implementation of various Turbo Decoders suffers from a large delay and high power consumption. For this reason, they are not suitable for many applications like mobile communication systems. In this paper, a comparative study has been made and various decoding algorithm used in SISO Turbo Decoders have been analyzed viz. MAP, Log-MAP, Max-Log-MAP and SOVA, to overcome this drawback. It presents the discussion of complexity and performance trade-offs of SISO Turbo decoders
A Survey Paper on Different Turbo Decoders and Their Comparison
In order to have reliable communication, channel coding is often employed. Turbo code as a powerful coding technique has been widely studied and used in communication systems. Turbo coding is an advanced forward error c o r r e c t i o n a l g o r i t h m . U l t i m a t e Performance that approaches the Shannon limit requires a new approach using iteratively run soft in/soft out (SISO) decoders called turbo decoders. However, the implementation of various Turbo Decoders suffers from a large delay and high power consumption. For this reason, they are not suitable for many applications like mobile communication systems. In this paper, a comparative study has been made and various decoding algorithm used in SISO Turbo Decoders have been analyzed viz. MAP, Log-MAP, Max-Log-MAP and SOVA, to overcome this drawback. This paper examines the principles of turbo coding and decoding algorithms and compare their BER performance.
Parallel and …, 2005
This paper describes low power, reconfigurable architectures for Turbo Decoder. Currently most of the reconfigurable solutions in research target reconfiguration between different convolution based decoders for example Viterbi-Sova or Sova-LogMap. The reconfigurable Turbo decoder array presented in this paper not only provides flexibility to choose between different constraint lengths, frame lengths and code rates but also different levels of quantization. Similarly, dynamic or static mapping of different algorithms can be done to meet various performance constraints in terms of reduced power, improved speed and different levels of error correction. The architecture can support channel decoding for most of the current communication systems.
Design and Implementation Different Types of Turbo Decoder with Various Parameters
International Journal of Computer Applications, 2017
This paper presents design and implementation of turbo code, after that many types of decoders are introduced with various many parameters such as(number of iteration, length of code, number of frame, type of decoding techniques, rate, generator polynomial and type of channel) get the Bit Error Rate (BER) for each case, and compare the results. This work in order to study the effect of each parameter on the performance of Turbo Code to specify the parameters that give the optimum performance of this codes. Finally turbo encoder implemented on FPGA device.
LOW COMPLEXITY TURBO DECODER WITH MODIFIED ACS
IAEME PUBLICATION, 2014
Error correcting codes are used to correct the data from the corrupted signal due to noise and interference. There are many error correcting codes. Among them turbo codes is considered to be the best because it is very close to the Shannon theoretical limit. The MAP algorithm is commonly used in the turbo decoder. Among the different versions of the MAP algorithm Constant log BCJR algorithm have less complexity and good error performance. The Constant log BCJR algorithm can be easily designed using look up table which reduces the memory consumption. The proposed Constant log BCJR decoder is designed to decode two blocks of data at a time, this increases the throughput. The complexity of the decoder is further reduced by the use of the add compare select (ACS) units and registers. The proposed decoder is simulated using Xilinx ISE and synthesized using Sparten3 FPGA and found out that Constant log BCJR decoder utilized less amount of memory and power than the LUT log BCJR decoder.