Implementation of a mobile phone module with redistributed chip packaging (original) (raw)
Related papers
Design & Development of a Large Die and Fine Pitch Wafer-Level Package for Mobile Applications
56th Electronic Components and Technology Conference 2006, 2006
Wafer level packaging offers the advantage of chip scale packaging with an efficient production approach. In addition to size, cost and ease of logistics make it as a main stream packaging solution for a single chip. Resulting saving in size, cost has also resulted in limitation of using conventional wafer level packaging for large die size and high IO devices. This paper reports the development of a wafer level package with 440 IOs, 400 microns pitch and 12 X 12 mm die size for mobile applications.
Design and development of a multi-die embedded micro wafer level package
2008
The primary trend in electronics industry is product miniaturization. Both design and manufacturing engineers are looking for ways to make products lighter, smaller, less expensive, and at the same time faster, more powerful, reliable, user-friendly, and functional. A partial list of today's "shrinking" products would include cellular phones, personal and sub-notebook computers, pagers, PCMCIA cards, camcorders, palmtop organizers, telecommunications equipment, and automotive components. With silicon chips continue integrating more functionality as per Moore's Law, the packaging is challenged to integrate and shrink. Chips First or Embedded Chip packaging is a revolutionary way to overcome these recent packaging integration challenges. Packaging researchers have worked on embedded packaging and developed newer way of embedding the chip. The PBGA replaced the lead frame based peripheral array packages, in which the die is electrically connected to circuit board (PCB) substrate by wire bonding or flip chip technology, before covering with molding compound. Embedded Wafer level packaging takes the next step, eliminating the PCB, as well as the need to use wire bonding or flip-chip bumps to establish electrical connection. This paper deals with the development embedding multiple dies at wafer level.
A 3-D packaging concept for cost effective packaging of MEMS and ASIC on wafer level
2009 European Microelectronics and Packaging Conference, 2009
Heterogeneous integration bridges the gap between nanoelectronics and its derived applications. Currently MEMS and their signal conditioning ASICs are produced and packaged at different industry sectors (different fabs). To reduce costs and enhance yield and performance at the same time this quite expensive way of packaging has to be modified. This paper presents a different packaging concept. It uses standard redistribution layer technology (RDL) to package thinned chips on a full wafer substrate e.g. thinned ASIC chips on a MEMS wafer. For this approach no Through Silicon Vias (TSV) are needed. Standard chips can be used without redesign. Only Known Good Dies (KGDs) are packaged with the cost benefit of wafer level technology. At the starting point for this type of packaging both ASIC and MEMS chips are still parts of full wafers. The wafer with the larger sized chips (e.g. MEMS chips) is used as a substrate for the further process steps. The wafer with the smaller sized chips (e.g. ASIC chips) is thinned down on wafer level to a thickness of 10µm to 40µm and diced. These thinned chips are glued onto the base wafer with a polymer layer (BCB from Dow Chemical). The polymer has been deposited and structured before gluing the next chip on top. After placement of the thinned chips the wafer is again coated with BCB to embed the chips. This polymer layer is photostructured to open contact pads on the base chips as well as on the embedded chips. The next step is the built-up of metal routing. Here a semi-additive process is used, which means electroplating on a sputter seed layer of TiW/Cu. This metal layer is followed by another polymer layer for passivation and acting as a solder mask. Then Under Bump Metallization (UBM) is applied again by electroplating. Finally Balling is done either by Ball Placement or by Solder Paste Printing. Now the wafer is diced and the full ASIC-MEMS package can be flip chiped onto a Printed Circuit Board (PCB). The technology will be demonstrated by the project RESTLES (Reliable System Level Integration of Stacked Chips on MEMS). RESTLES will integrate technologies like silicon MEMS, ASIC, wafer thinning, chip stacking and flip chip to one packaged chip stack at die scale. The influence of the heterogeneous stack on performance and control mechanisms to eliminate parasitic effects will be investigated.
Module miniaturization by ultra thin package stacking
2010
The scope of the European project TIPS (Thin Interconnected Package Stacks) is the fabrication of ultra thin packages for electronic components and the subsequent stacking and interconnection of those packages to form highly compact modules. In the first part of this paper approaches to fabricate ultra thin 10 × 10 mm packages by embedding technologies for chips into printed circuit board environments will be discussed. One technology uses commercial flexible printed circuit board substrates (polyimide sandwiched in Cu layers) and respective fabrication processes. After initial patterning of the Cu the chips are die bonded to the flex substrates and subsequently laminated into build up layers. Electrical contact between the chip and a fan out routing on the outer layer of the package are made by micro via formation, electroplating and wet chemical structuring of the metal layers. The thickness of the embedded components is constricted to 50 μm in order to constrain the package thicknesses to a maximum of 100 μm with this approach. The alternative approach, the ultra thin chip package (UTCP) technology, aims at package thicknesses around 60 μm. In this case 20 μm thick chips are die-bonded to thin polyimide layer. A photo-definable polyimide is then applied over the assembled chips by spin-on technique. Contact pads are opened by exposure and development of the polyimide, followed by metal sputtering, electroplating and etching. In this approach the thickness of embedded components is typically 20-30 μm and final package thickness is in the range of 60 μm. In both approaches the packages are fabricated as batches consisting of 150 × 150 mm sheets of flex substrates. Stacking of individual packages can be performed in an automated package by package placement process using a frame as alignment tool and typical flexible printed circuit boards adhesives. In this way only known-good-packages are stacked in o- - rder to minimize yield loss. However, a more straight forward process is stacking of the packages using fabrication batches and established multilayer printed circuit board technologies. The disadvantage is the potential yield loss if one of the packages in a stacked layer is faulty. For either type of stacking process the individual stacks have to be milled out of the stack fabrication batch. Development issues, design considerations and results of first fabrication runs will be presented and discussed.
2011
Two embedded micro-wafer-level packages (EMWLP) with 1) laterally placed and 2) vertically stacked thin dies are designed and developed. Three-dimensional stacking of thin dies is demonstrated as progressive miniaturization driver for multi-chip EMWLP. Both the developed packages have dimensions of 10 mm × 10 mm × 0.4 mm and solder ball pitch of 0.4 mm. As part of the development several key processes like thin die stacking, 8-in wafer encapsulation using compression molding, low-temperature dielectric with processing temperature less than 200°C have been developed. The EMWLP components success fully pass 1000 air to air thermal cycling (-40°C to 125°C), unbiased highly accelerated stress testing (HAST) and moisture sensitivity level (MSL3) tests. Developed EMWLP also show good board level TC (>; 1000 cycles) and drop test reliability results. Integration of thin film passives like inductors and capacitors are also demonstrated on EMWLP platform. Developed thin film passives show a higher Q-factor when compared to passives on high resistivity silicon platform. Thermo-mechanical simulation studies on developed EMWLP demonstrate that systemic control over die, RDL, and package thicknesses can lead to designs with improved mechanical reliability.
Universal Service Systems for Scalable Copper Packaging of Discrete Circuit Components
International Journal of Circuits, Systems and Signal Processing, 2021
In the decade of digital electronics, no matter what type is, high-value, high-complexity, high-performance devices (such as the main microprocessor core in smart phones) is undoubtedly crucial. However, simple discrete circuit components (such as capacitors, resistors, diodes, transistors, etc.) are also essential for mobile phones. In order to continue to increase functionality and reliability, reduce size and power consumption, reduce costs, and any function we seek in electronic equipment, there is always the basic principle of squeezing everything onto the same semiconductor chip. However, in some unavoidable situations, not all circuit components can run on the same chip. This service system uses a copper substrate as the core material for packaging, and can package chips with high bonding density. It provides a universal service platform for packaged products called: Scalable Universal Copper-based Packaging (CopperPak) service system. This service system is attributed to cop...
Technology Requirements for Chip-On-Chip Packaging Solutions
Proceedings Electronic Components and Technology, 2005. ECTC '05., 2005
The trend towards smaller, lighter and thinner products requires a steady miniaturization which has brought-up the concept of Chip Scale Packaging (CSP). The next step to reduce packaging cost was the chip packaging directly on the wafer. Wafer Level Packaging (WLP) enables the FC assembly on PWB without interposers. New and improved microelectronic systems require significant more complex devices which could limit the performance due to the wiring of the subsystems on the board. 3-D packaging using the existing WLP infrastructure is one of the most promising approaches. Stacking of chips for chip-on-chip packages can be done by wafer-to-wafer stacking or by chip-to-wafer stacking which is preferable for yield and die size considerations. This chip-on-chip packaging requires a base die with redistribution traces to match the I/O layout of both dice. This allows the combination of the performance advantage of flip chip with the options of WLP. To avoid the flip chip bonding process the thin chip integration (TCI) concept can be used. Key elements of this approach are extremely thin ICs (down to 20 µm thickness) which are incorporated into the redistribution. This technology offers excellent electrical properties of the whole microelectronic system. The focus of this paper will be the technology requirements for the realization of different kinds of chip-onchip packages.
Characterization of Substrate Materials for System-in-a-Package Applications
Journal of Electronic Packaging, 2004
System-in-a-Package (SiP) aims to integrate the entire system functions within a systemlevel package containing multiple ICs and other components interconnected in a highdensity substrate. A structure based on the SiP concept is proposed in this paper. Based on this SiP structure, four substrate candidates, namely FR4, liquid crystal polymer (LCP), teflon (PTFE) and low temperature co-fired ceramic (LTCC) were compared by assessing and measuring their mechanical reliability, electrical performance and environmental influence. First, to evaluate long-term reliability, the 3D finite element method (FEM) was used to calculate the stress distribution and warpage of the whole package. Both threepoint bending and cooling in the manufacturing process were taken into consideration. The LCP has a coefficient of thermal expansion (CTE) close to that of the silicon chip, and a Young's module close to that of FR4, which gave the best reliability in both bending and cooling situations. Next, the dielectric constants and the loss tangent for the four substrates were evaluated in the electrical performance investigation. The LCP has a low relative dielectric constant and a low dissipation factor for the frequency range 1 GHz to 35 GHz, making it a good substrate for high frequency applications. An environmental assessment included several environmental impact categories; this assessment indicated that LCP is the most environmentally acceptable substrate.
Process technology for the fabrication of a Chip-in-Wire style packaging
2008 58th Electronic Components and Technology Conference, 2008
In this contribution, progress on Chip-in-Wire packaging will be presented. The basic principle behind this concept is that small chips are interconnected and embedded in a flexible (and possibly stretchable) material so that a resulting 1D array of interconnected dies can be formed. At the end of the process, the structures can be released so that a freestanding "wire" of interconnected chips is fabricated.