A 0.8-μm CMOS, 622 Mb/s SDH/SONET communication system (original) (raw)
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A 40-Gb/s serial link transceiver in 28-nm CMOS technology
2014 Symposium on VLSI Circuits Digest of Technical Papers, 2014
A 40 Gb/s serial link interface is presented that includes four lanes of transceiver optimized for chip-to-chip communication while compensating for 20 dB of channel loss. Transmit equalization consists of a 2-tap feed-forward equalizer (FFE) while receive equalization includes a 2-tap FFE using a transversal filter, a 3-stage continuous-time linear equalizer with active feedback, and discrete-time equalizers consisting of a 17-tap decision feedback equalizer (DFE) and a 3-tap sampled FFE. The receiver uses quarter-rate double integrate-and-hold sampling. The clock and data recovery (CDR) unit uses a split-path CDR/DFE design which facilitates wider bandwidth and lower jitter simultaneously. A phase detection scheme that filters out edges affected by residual inter-symbol interference allows recovering a low-jitter clock from a partially-equalized eye. A fractional-N PLL is implemented for frequency offset tracking. Combining these techniques, the digital CDR recovers a stable 10 GHz clock from an eye containing 0.8 UI p-p input jitter and achieves 1-10 MHz of tracking bandwidth. The transceiver achieves horizontal and vertical eye openings of 0.27 UI and 120 mV, respectively, at BER = 10-9. The quad SerDes is realized in 28 nm CMOS technology. Amortizing common blocks, it occupies 0.81 mm per lane and achieves 23.2 mW/Gb/s power efficiency at 40 Gb/s. Index Terms-Active feedback continuous-time linear equalizer, chip-to-chip communications, current-integrating DFE summer, decision feedback equalizer (DFE), distributed ESD protection structure, high-speed serial link (SerDes), receive-side feed-forward equalizer (RX-FFE), split-path clock and data recovery (split-path CDR), transversal filter, wireline transceiver.
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In this article, an asynchronous serial transceiver that is capable of transmitting and receiving an auxiliary data stream concurrently with the primary data stream is described. The transceiver instantiates the auxiliary data stream by modulating the phase of the primary data without affecting the primary channel transmission and recovery mechanisms. Standard receiver interoperability is maintained since the auxiliary data appear as primary data jitter. Analysis of the proposed transceiver and considerations of the system parameters are included and can be used to determine how such an auxiliary channel is implemented. The proposed transceiver with the auxiliary channel can be widely used in many data communication applications such as for transmitting signatures for authentication or other control information, steganography, or additional data in an existing serial link. A prototype transceiver, implemented in a 65-nm CMOS process, demonstrates the proposed concept with an 80-Mb/s auxiliary channel in a 2.56-Gb/s asynchronous serial link.
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IEEE Journal of Solid-state Circuits, 2005
A transceiver capable of 6.25-Gb/s data transmission across legacy communications equipment backplanes is described. To achieve a bit error rate (BER) 10 15 , transmit and receive equalization that can compensate up to 20 dB of channel loss is employed to remove intersymbol interference (ISI) resulting from finite channel bandwidth and reflections. The transmit feed-forward equalizer (FFE) uses a four-tap symbol-spaced programmable finite impulse response (FIR) filter followed by a 4-bit digital-toanalog converter (DAC) that drives a 50transmission line. The receiver uses a half-baud-rate adaptive decision feedback equalizer (DFE) that cancels the first four symbol-spaced taps of postcursor ISI without use of speculative techniques. Both the transmitter and receiver use an LC-oscillator-based phase-locked loop (PLL) to provide low jitter clocks. Techniques to minimize the complexity of the FIR and DFE implementations are described. The transceiver is designed to be integrated in a standard ASIC flow in a 0.13m digital CMOS technology. System measurements indicate the ability to transmit and recover data eyes that have been fully closed due to crosstalk and signal loss. He is currently working on high-speed/high-resolution analog-to-digital converters. His interests are in input/outputs (I/Os) and equalization, clock and data recovery, data conversion, and phase-locked loop design.
2018
A new asynchronous serial transceiver is proposed that is capable of transmitting and receiving a secondary data stream along with the primary data stream on a single asynchronous serial link. The proposed transceiver embeds the secondary data stream by modulating the phase of the primary data in accordance with it. The receiver recovers both the primary and secondary data simultaneously. In a standard receiver, which is not equipped with the phase demodulation capability, the secondary data appears as jitter of the primary data. The jitter caused by the secondary data still falls within the jitter budget of the transceiver, and having this much jitter would not adversely affect the functionality of the primary data recovery. The proposed system can be widely used in many data communication applications such as for transmitting a hidden signature for data authentication, or as control and/or additional data in an existing serial link. A prototype transceiver, implemented in a 65 nm CMOS process, demonstrates the proposed concept with 2.56 Gbps primary data and 80 Mbps secondary data channels.
A 0.7 μm CMOS clock recovery circuit for 622 Mb/s SDH systems
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A 34 Gb/s Distributed 2:1 MUX and CMU Using 0.18 muhboxmmuhbox mmuhboxm CMOS
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A 34 Gb/s 2:1 serializer consisting of a CMOS MUX and CMU using a 0.18 mu m SiGe BiCMOS process is presented. The serializer is based on distributed amplifier topology realized using spiral inductors. The circuit also includes an on-chip 2-channel 2(7) -1 PRBS generator. The 34 Gb/s serial output has single-ended voltage swing of 380 mV with rise/fall time of 13 ps, and measured ISI is less than 5 ps p-p.