Gate line edge roughness amplitude and frequency variation effects on intra die MOS device characteristics (original) (raw)
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Full 3D Statistical Simulation of Line Edge Roughness in sub-100nm MOSFETs
Line Edge Roughness (LER), caused by tolerances inherent to materials and tools used in lithography processes, is not a new phenomenon. Yet, the imperfections caused by LER have caused little worry over the years since the critical dimensions of MOSFETs were almost two orders of magnitude larger than the roughness. However, as the aggressive scaling of Si-MOSFETs continues to the sub-100 nm regime, LER does not diminish but constitutes an increasingly larger fraction of the gate length. Indeed, at the end of the SIA Roadmap [1], MOSFETs with gate length as small as 20 nm are anticipated, making LER one of the critical problems for ULSI, where millions of devices must operate in very strict margins on a single chip.
Analysis of Statistical Fluctuations due to Line Edge Roughness in sub-0.1μm MOSFETs
Simulation of Semiconductor Processes and Devices 2001, 2001
We present a full-3D statistical analysis of line edge roughness (LER) in sub-0.1 µm MOSFETs. The modelling approach for line edges and the parameters used in the analysis take into account the statistical nature of the roughness. The results indicate that intrinsic fluctuations in MOSFETs due to LER become comparable in size to random dopant effects and can seriously inhibit scaling below 50 nm.
2008
The threshold voltage (V th ) of a nanoscale transistor is severely affected by random dopant fluctuations and line-edge roughness. The analysis of these effects usually requires atomistic simulations that are too expensive in computation for statistical circuit design. In this work, we develop an efficient SPICE simulation method and statistical transistor model that accurately predict threshold variation as a function of dopant fluctuations and gate length change caused by sub-wavelength lithography and the gate etching process. By understanding the physical principles of atomistic simulations, we (a) identify the appropriate method to divide a non-uniform gate into slices in order to map those fluctuations into the device model; (b) extract the variation of V th from the strong-inversion region instead of the leakage current, benefiting from the linearity of the saturation current with respect to V th ; and (c) propose a compact model of V th variation that is scalable with gate size and the amount of dopant and gate length fluctuations. The proposed SPICE simulation method is fully validated against atomistic simulation results. Given the post-lithography gate geometry, this approach correctly models the variation of device output current in all operating regions. Based on the new results, we further project the amount of V th variation at advanced technology nodes, helping shed light on the challenges of future robust circuit design.
IEEE Transactions on Electron Devices, 2013
Investigations on device variability for three different emerging field-effect transistor (FET) technologies are performed to determine the statistical dependence or independence of line edge roughness (LER) and random dopant fluctuation (RDF) variability mechanisms. The device candidates include standard inversion-mode (IM) FinFETs, junctionless (JL) FinFETs, and tunnel FETs (TFETs) designed for sub-32-nm generations. Using technology computer-aided design simulations, extracted standard deviations in linear and saturation threshold voltages (V T,lin and V T,sat), ON-state current (I ON), OFF-state current (I OFF), subthreshold swing (SS), and draininduced barrier lowering (DIBL) are compared for the cases: 1) when LER and RDF are separately modeled during device simulations and assumed to combine in an uncorrelated fashion, and 2) when LER and RDF are simultaneously modeled in device simulations and no assumption is made about their interaction. After performing the comparisons for each FET technology, we find that LER and RDF cannot be considered independent for IM-FinFETs and TFETs, but can be for JL-FinFETs. The different outcomes are related to local versus distributed variability dependencies in each transistor type. Our conclusions reinforce the need for more comprehensive treatment of variability effects to provide accurate estimations of expected device variability in junction-based FETs.
nrn Il 10 nm 40nm poly " nm~S i 10 nrn / Si !.i-7nm tox >< 0 lsox=20 nm Si 50 nm NBU LK = \018cm·3 II. ApPROACH The approach we propo se require s the identification of the relevant quantities that translate process variability into variability of electrical parameters. It involves the following three steps: Template 32 nm Template 22 nm 10nm \0 Figure I : Template structures for the 32 nm UTB SOl MOS FET (left) and the 22 nm double-gat e MOSF ET (right). The device is symmetrical. Doping profiles for source and drain are described in fll). The effective oxide thickn ess t ox is 1.2 nm for the 32 nm temp late and 1.1 nm for the 22 nm template. 50
Modeling line edge roughness effects in sub 100 nanometer gate length devices
2000
A fast method to estimate the effects of line edge roughness is proposed. This method is based upon the use of multiple 2D device “slices” sandwiched together to form a MOS transistor of a given width. This method was verified to yield an accurate representation of rough edge MOS transistors through comparisons to full three dimensional simulations. A subsequent statistical study shows how the variation in line edge roughness affects the values and variances of several key device parameters
2015 International Conference on Noise and Fluctuations (ICNF), 2015
In this paper, a thorough statistical investigation of low frequency noise (LFN) variability in MOSFETs is presented. In smaller-sized devices, noise fluctuations are areadominated. In moderate-to large-sized transistors (Area >> 1μm 2 ), normalized noise fluctuations are roughly independent of area, but show a distinct degradation towards weak inversion (subthreshold). A new model is proposed for the gatevoltage dependence of 1/f noise variations in moderately-sized transistors. We show that the gate-voltage dependence may be related to transconductance-to-current ratio g m /I D . Extensive measurements of low frequency noise variability in experimental 180nm CMOS confirm the newly proposed model.
Determination of the line edge roughness specification for 34 nm devices
Digest. International Electron Devices Meeting,, 2002
The impact of gate line edge roughness (LER) on 70 nm MOS devices was measured experimentally and used to validate an enhanced statistical technique for evaluating LER effects on devices. The technique was used to determine that LER in 34 nm devices will need to be limited to 3 nm. Effect of LER spectrum on wide and narrow devices is discussed, as well as an approach for correcting experimental current measurements for LER.
Journal of Physics: Conference Series, 2006
Variability in device characteristics will affect the scaling and integration of next generation nano-CMOS transistors. Intrinsic parameter fluctuations introduced by random discrete dopants, line edge roughness and oxide thickness fluctuations are among the most important sources of variability. In this paper the variability introduced by the above sources is studied in a set of well scaled MOSFETs with channel lengths of 25, 18, 13, and 9 nm. The effect of each source of intrinsic parameter fluctuation is quantified and compared. The random discrete dopants are responsible for the strongest variations followed closely by line edge roughness. The statistical independence of the different sources of fluctuations is also studied in the case of a 35 nm MOSFET.