Modeling and characterization of contact-edge roughness for minimizing design and manufacturing variations (original) (raw)
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Proceedings of Spie the International Society For Optical Engineering, 2010
Despite intensive attention on line-edge roughness (LER), contact-edge roughness (CER) has been relatively less studied. Contact patterning is one of the critical steps in a state-of-the-art lithography process; meanwhile, the design rule shrinking leads to larger CER in contact holes. Since source/drain (S/D) contact resistance depend on contact area and shape, larger CER results in significant change in a device current. In this paper, we first propose a CER model based on power spectral density function which is a function of RMS edge roughness, correlation length, and fractal dimension. Then, we present a comprehensive contact extraction methodology for analyzing process-induced CER effects on circuit performance. In our new contact extraction model, we first dissect the contact with a same distance, and then calculate the effective resistance considering both the shape weighting factor and the distance weighting factor for stress induced CMOS cells. Using the results of CER, we analyze the impact of CER variation on the S/D contact resistance and the device saturation current. Results show that when the rms value of CER is 10nm, the S/D contact resistance and the device saturation current can vary by as much as 57.8% and 2.1%, respectively.
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2000
A fast method to estimate the effects of line edge roughness is proposed. This method is based upon the use of multiple 2D device “slices” sandwiched together to form a MOS transistor of a given width. This method was verified to yield an accurate representation of rough edge MOS transistors through comparisons to full three dimensional simulations. A subsequent statistical study shows how the variation in line edge roughness affects the values and variances of several key device parameters
Determination of the line edge roughness specification for 34 nm devices
Digest. International Electron Devices Meeting,, 2002
The impact of gate line edge roughness (LER) on 70 nm MOS devices was measured experimentally and used to validate an enhanced statistical technique for evaluating LER effects on devices. The technique was used to determine that LER in 34 nm devices will need to be limited to 3 nm. Effect of LER spectrum on wide and narrow devices is discussed, as well as an approach for correcting experimental current measurements for LER.
Journal of Computational Electronics, 2006
Understanding how lithographic material and processing, affect linewidth roughness (LWR), and finally device operation is of immense importance in future scaled MOS transistors. The goal of this work is to determine the impact of LWR on device operation and to connect material and process parameters with it. To this end, we examine the effects of photoresist polymer length and acid diffusion length on LWR and transistor performance. Through the application of a homemade simulator of the lithographic process, it is shown that photoresists with small polymer chains and small acid diffusion lengths form lines with low LWR and thus lead to transistors with more reliable electrical performance.
Modeling of layout aware line-edge roughness and poly optimization for leakage minimization
2011
Line-edge roughness (LER) highly affects the device saturation current and leakage current, which leads to serious device performance degradation. In this paper, we propose the first layout-aware LER model where LER is highly related to the lithographic aerial image fidelity and neighboring geometric proximity. With our new LER model, we perform robust LER aware poly layout optimization to minimize the degradation of device performance, in particular leakage current. The results on 32-nm node standard cells show average 91.26% reduction of leakage current and 4.46% improvement of saturation current at the worst case process corner despite 8.86% area penalty.
Experimental investigation of the impact of line-edge roughness on MOSFET performance and yield
2003
This work experimentally investigates the impact of lineedge roughness (LER) on the intrinsic transistor performance of the MOS transistor. Examined gate lengths range down to 50 nm. To emphasize the impact of LER, transistors with extra rough poly gates are created by e-beam lithography. Assumptions of models, that describe the effects of LER, are tested on transistors with sinusoidal gate-shapes. For the first time, the impact of LER on transistor yield is reported.
A simulation study on the impact of lithographic process variations on CMOS device performance
Proceedings of SPIE, 2008
In this paper, we demonstrate how a direct coupling of a lithography simulation program and a semiconductor device simulation tool can be used to investigate the impact of lithographic process variations on nano-scaled CMOS devices. In contrast to conventional evaluation criteria such as process windows, mask error enhancement factor (MEEF), or CD (critical dimension) uniformity, the lithography process is regarded in a more holistic fashion as a means to an end. As a consequence, the ultimate figure of merit is determined by the performance of the device. Lithography simulations are conducted using a rigorous EMF solver for the computation of the mask nearfield. TCAD process and device simulations are performed for an ultra thinned body fully depleted silicon on insulator (UTB FD-SOI) nMOSFET, with a physical gate length of 32 nm. Electrical parameters such as on-and offcurrent, threshold voltage, sub-threshold slope, gate-capacitance, and contact resistances are computed and extracted. The impact of lithographic process variations on the electrical behavior of the target device is surveyed and illustrated. Moreover, we present an adjusted lithography process window defined by the electrical behavior of the device. In addition to a discussion of the obtained results, this paper also focuses on the software design aspects of interfacing a lithography simulation environment with a device simulator. The steps involved in extracting parameters and transferring them from one program to the other are explained, and further automation capabilities are suggested. Moreover, it is illustrated how this approach can be extended towards an integrated litho/device process optimization procedure.
A simulation study on the impact of lithographic process variations on CMOS device performance
Optical Microlithography XXI, 2008
In this paper, we demonstrate how a direct coupling of a lithography simulation program and a semiconductor device simulation tool can be used to investigate the impact of lithographic process variations on nano-scaled CMOS devices. In contrast to conventional evaluation criteria such as process windows, mask error enhancement factor (MEEF), or CD (critical dimension) uniformity, the lithography process is regarded in a more holistic fashion as a means to an end. As a consequence, the ultimate figure of merit is determined by the performance of the device.
Contact Edge Roughness: Characterization and modeling
Microelectronic Engineering, 2011
In this paper, first we clarify the differences between Contact Edge Roughness (CER) and Line Edge Roughness (LER) emanating from the circular form of the contact edge. Then, we investigate the effects of these differences on the characterization of the spatial and frequency aspects of CER: We define the heightheight correlation function for a circular contact hole, use its shape to understand low-frequency deformations of contact holes from the ideal circle, generate model contact holes with predetermined CER and deformations, and finally study the relation between CER and Critical Dimension (CD) variation of the contact holes on a wafer.
A guideline for evaluating LER and total procedure to estimate effects of measured LER on device performance were proposed. Spatial-frequency distributions of LER in various resist materials were investigated and general characteristics of spatial-frequency distribution of were obtained. Measurement parameters for accurate LER measurement can be calculated according to the guideline. Measured line-width distribution was used to predicting degradation and variation in MOS transistor performance using the two-dimensional device simulation. Effect of long-period component of LER was clarified as well as short-period component.