Modeling and characterization of contact-edge roughness for minimizing design and manufacturing variations in 32-nm node standard cell (original) (raw)
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Journal of Micro/Nanolithography, MEMS, and MOEMS, 2010
Despite intensive attention on line-edge roughness (LER), contact-edge roughness (CER) has been relatively less studied. Contact patterning is one of the critical steps in a state of the art lithography process; meanwhile, design rule shrinking leads to larger CER in contact holes. Since source/drain (S/D) contact resistance depends on contact area and shape, larger CER results in significant change in a device current. We first propose a CER model based on the power spectral density function, which is a function of rms edge roughness, correlation length, and fractal dimension. Then, we present a comprehensive contact extraction methodology for analyzing process-induced CER effects on circuit performance. In our new contact extraction model, we first dissect the contact with a same distance, and then calculate the effective resistance considering both the shape weighting factor and the distance weighting factor for stress-induced complementary metal-oxide semiconductor (CMOS) cells. Using the results of CER, we analyze the impact of both random CER and systematic variation on the S/D contact resistance, and the device saturation current. Results show that the S/D contact resistance and the device saturation current can vary by as much as 135.7 and 4.9%, respectively.
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2000
A fast method to estimate the effects of line edge roughness is proposed. This method is based upon the use of multiple 2D device “slices” sandwiched together to form a MOS transistor of a given width. This method was verified to yield an accurate representation of rough edge MOS transistors through comparisons to full three dimensional simulations. A subsequent statistical study shows how the variation in line edge roughness affects the values and variances of several key device parameters
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Digest. International Electron Devices Meeting,, 2002
The impact of gate line edge roughness (LER) on 70 nm MOS devices was measured experimentally and used to validate an enhanced statistical technique for evaluating LER effects on devices. The technique was used to determine that LER in 34 nm devices will need to be limited to 3 nm. Effect of LER spectrum on wide and narrow devices is discussed, as well as an approach for correcting experimental current measurements for LER.
A simulation study on the impact of lithographic process variations on CMOS device performance
Proceedings of SPIE, 2008
In this paper, we demonstrate how a direct coupling of a lithography simulation program and a semiconductor device simulation tool can be used to investigate the impact of lithographic process variations on nano-scaled CMOS devices. In contrast to conventional evaluation criteria such as process windows, mask error enhancement factor (MEEF), or CD (critical dimension) uniformity, the lithography process is regarded in a more holistic fashion as a means to an end. As a consequence, the ultimate figure of merit is determined by the performance of the device. Lithography simulations are conducted using a rigorous EMF solver for the computation of the mask nearfield. TCAD process and device simulations are performed for an ultra thinned body fully depleted silicon on insulator (UTB FD-SOI) nMOSFET, with a physical gate length of 32 nm. Electrical parameters such as on-and offcurrent, threshold voltage, sub-threshold slope, gate-capacitance, and contact resistances are computed and extracted. The impact of lithographic process variations on the electrical behavior of the target device is surveyed and illustrated. Moreover, we present an adjusted lithography process window defined by the electrical behavior of the device. In addition to a discussion of the obtained results, this paper also focuses on the software design aspects of interfacing a lithography simulation environment with a device simulator. The steps involved in extracting parameters and transferring them from one program to the other are explained, and further automation capabilities are suggested. Moreover, it is illustrated how this approach can be extended towards an integrated litho/device process optimization procedure.
A simulation study on the impact of lithographic process variations on CMOS device performance
Optical Microlithography XXI, 2008
In this paper, we demonstrate how a direct coupling of a lithography simulation program and a semiconductor device simulation tool can be used to investigate the impact of lithographic process variations on nano-scaled CMOS devices. In contrast to conventional evaluation criteria such as process windows, mask error enhancement factor (MEEF), or CD (critical dimension) uniformity, the lithography process is regarded in a more holistic fashion as a means to an end. As a consequence, the ultimate figure of merit is determined by the performance of the device.
Experimental investigation of the impact of line-edge roughness on MOSFET performance and yield
2003
This work experimentally investigates the impact of lineedge roughness (LER) on the intrinsic transistor performance of the MOS transistor. Examined gate lengths range down to 50 nm. To emphasize the impact of LER, transistors with extra rough poly gates are created by e-beam lithography. Assumptions of models, that describe the effects of LER, are tested on transistors with sinusoidal gate-shapes. For the first time, the impact of LER on transistor yield is reported.
Modeling of layout aware line-edge roughness and poly optimization for leakage minimization
2011
Line-edge roughness (LER) highly affects the device saturation current and leakage current, which leads to serious device performance degradation. In this paper, we propose the first layout-aware LER model where LER is highly related to the lithographic aerial image fidelity and neighboring geometric proximity. With our new LER model, we perform robust LER aware poly layout optimization to minimize the degradation of device performance, in particular leakage current. The results on 32-nm node standard cells show average 91.26% reduction of leakage current and 4.46% improvement of saturation current at the worst case process corner despite 8.86% area penalty.
Journal of Computational Electronics, 2006
Understanding how lithographic material and processing, affect linewidth roughness (LWR), and finally device operation is of immense importance in future scaled MOS transistors. The goal of this work is to determine the impact of LWR on device operation and to connect material and process parameters with it. To this end, we examine the effects of photoresist polymer length and acid diffusion length on LWR and transistor performance. Through the application of a homemade simulator of the lithographic process, it is shown that photoresists with small polymer chains and small acid diffusion lengths form lines with low LWR and thus lead to transistors with more reliable electrical performance.
Full 3D Statistical Simulation of Line Edge Roughness in sub-100nm MOSFETs
Line Edge Roughness (LER), caused by tolerances inherent to materials and tools used in lithography processes, is not a new phenomenon. Yet, the imperfections caused by LER have caused little worry over the years since the critical dimensions of MOSFETs were almost two orders of magnitude larger than the roughness. However, as the aggressive scaling of Si-MOSFETs continues to the sub-100 nm regime, LER does not diminish but constitutes an increasingly larger fraction of the gate length. Indeed, at the end of the SIA Roadmap [1], MOSFETs with gate length as small as 20 nm are anticipated, making LER one of the critical problems for ULSI, where millions of devices must operate in very strict margins on a single chip.
2010
Lithography and stress variations are two dominant effects that significantly impact the functionality and performance of circuit designs at 45nm and below. Variabilityaware circuit analysis methods have been introduced into the circuit design flow as one approach for implementing Design For Manufacturability (DFM) tools. These tools bridge the chip design implementation and manufacturing know-how to deliver high-value equivalent scaling advances. This paper presents an automated DFM framework that evaluates the digital design awareness of the process and physical layout effects on design performance. This study is applied on standard cell libraries and on critical paths of digital designs to monitor their differences in the physical and electrical parameters due to lithography and stress variations. An industrial FIR (Finite Inpulse Response) circuit designed in 45nm technology is used in our experiment. The results show the differences in the timing of the critical paths between the timing simulated from the standard netlist (without context awareness) and the timing simulated by using a randomly generated/actual design context aware netlist. In addition our study indicates that the variation of the timing of the critical paths differs from one industrial library to another. This shows the importance of having a variability-aware method that qualifies the libraries to be adopted for circuit designs.