High speed Si/SiGe and Ge/SiGe MODFETs (original) (raw)

Impact of device geometry and doping strategy on linearity and RF performance in Si/SiGe MODFETs

Microelectronics Reliability, 2004

Based on careful calibration in respect of 70 nm n-type strained Si channel Si/SiGe modulation doped FETs (MODFETs) fabricated by Daimler Chrysler, numerical simulations have been used to study the impact of the device geometry and various doping strategies on device performance and linearity. Both the lateral and vertical layer structures are crucial to achieve high RF performance or high linearity. The simulations suggest that gate length scaling helps to achieve higher RF performance, but degrades the linearity. Doped channel devices are found to be promising for high linearity applications. Trade-off design strategies are required for reconciling the demands of high device performance and high linearity simultaneously.

A Model for SiGe MODFETs with Improved Large-Signal Quality and Frequency Range

2002

A new, analytic large-signal model for N-channel SiGe Modulation Doped Field Ef-fect Transistors (MODFETs) is presented. The model is based on a non-linear equivalent circuit and can be employed to fit the characteristics in the sub-threshold, linear and saturation operating region from DC to high frequencies. In addition to the non-linear I ds current source, gate/drain-and gate/source capacitance elements, it contains a dispersion model to account for the observed low-frequency dispersion effects in the devices.

Optimizations of sub-100 nm Si/SiGe MODFETs for high linearity RF applications

2003 IEEE Conference on Electron Devices and Solid-State Circuits (IEEE Cat. No.03TH8668)

Based on careful calibration in respect of 70nm Mype strained Si channel SZiiGe modulation doped FETs (MODFETs) fabricaied by Daimler ChrysIer, numerical simulations have been used to study the impact of the device geometry and various doping straiegies on device performance and Iineariw. The devicegeometry is sensitive to both I W performance and device linearify. Doped channel devices are found to be promising for high linea@ applications. Trade-off design strategies are required far reconciling the demands of high device performance and high Iineariry simultaneously. The simul&'ons aIso suggest that gate lengih scaling helps to achieve higher RF performance, but decreases the Iinearig.

Noise behavior of SiGe n-MODFETS

Materials Science in Semiconductor Processing, 2005

This paper presents an investigation of the low-frequency noise properties of SiGe-based on n-MODFETs through the characterization of both the gate current noise and the drain current noise, including their correlation. Measurements vs. bias and gate geometry have shown that this noise is generated through mobility fluctuations or carrier diffusion at the gate terminal when carrier number fluctuations are involved for drain current fluctuations. Residual phase noise measurements have shown that the up-conversion effect mainly occurs on the drain current noise.

High-Performance SiGe MODFET Technology

MRS Proceedings, 2004

ABSTRACTAn overview of SiGe modulation-doped field-effect transistor (MODFET) technology is provided. The layer structures and mobility enhancements for both p- and n-channel modulation-doped quantum wells are described and compared to mobilities in Si/SiO2 inversion layers. Next, previous results on high-performance n- and p-MODFETs fabricated at IBM and elsewhere are reviewed, followed by recent results on laterally-scaled Si/SiGe n-MODFETs with gate lengths as small as 70 nm. We conclude with a discussion of the materials issues for the future vertical and lateral scaling of SiGe MODFETs.

Microwave Noise Performance and Modeling of SiGe-Based HFETs

IEEE Transactions on Electron Devices, 2005

Microwave noise performance of SiGe-based heterostructure field effect transistors (HFETs) is presented. Noise parameters for devices with buried channel fabricated on several virtual substrates are discussed. The impact of such strain relieved buffers on device noise performance is estimated by a proper noise de-embedding technique. Then, the noise properties measured in the 2.5-18-GHz frequency range are compared with those of other technologies. Noise parameters of SiGe HFETs are simulated using Pospieszalskis and Van Der Ziel's noise models. Some detrimental effects like access resistances and self-heating effects that negatively impact the microwave noise behavior are discussed and some alternatives to overwhelm them are proposed.

Gate Length Scaling in High fMAX Si/SiGe n-MODFET

32nd European Solid-State Device Research Conference, 2002

The performances of strained channel Si/Si 0.6 Ge 0.4 n-MODFETs as a function of gatelength have been investigated experimentally at 300K. The direct-current, microwave and noise performances of devices with gatelengths ranging from 0.5 µm to 0.1 µm are presented. Maximum oscillation frequency f MAX of 158 GHz is obtained for a 0.1 X 100 µm with f T = 42 GHz and a minimum noise figure NF min = 0.5 dB at 2.5 GHz showing the potential of SiGe technology. The dependence of small signal, and noise parameters on gatelength and biases has been analyzed to assess the impact of non stationary transport and of short channel effects on the device behavior.

High-performance SiGe pMODFETs grown by UHV-CVD

1999 Symposium on High Performance Electron Devices for Microwave and Optoelectronic Applications. EDMO (Cat. No.99TH8401), 1999

The fabrication and characterization of 0.1 ym-gate-length SiGe pMODFETs fabricated on UHV-CVD-grown heterostructures with various novel layer structure configurations are reported. We have fabricated Ge/Sio,4Geo,6 pMODFETs with peak extrinsic transconductance (gmeXt) values as high as zyx 488 mS/mm at room temperature. These devices also displayed a unity current gain cutoff frequency ( f T ) of 42 GHz and maximum frequency of oscillation (f-) of 86 GHz. We have also investigated the performance of Sio.zGe~.~/Sio.,Geo.3 pMODFETs on silicon-on-sapphire (SOS) substrates. These devices exhibited dc transconductances as high as g,, = 377 mS/mm, and had values offr = 49 GHz and fm = 95 GHz. The first high-frequency noise characterization of SiGe MODFETs has also been performed. Sio.~Geo.~/Sio.6~Geo.3~ pMODFETs grown on high-p Si substrates produced minimum

Design of nearly body-effect free Si/SiGe MODFETs

2000

DC transfer characteristic measurements have been carried out on one n-channel Si/SiGe MODFETs with a MOS gate at three different substrate biases. For our layer structure, electrons are supplied into the strained Si quantum well (QW) from the top heavily doped layer and below the QW is non-intentionally doped (setback). Here, we numerically studied the setback layer, for which the doping can be systematically designed to reduce the influence of the substrate bias on the threshold voltage (V TH ) shift. By inserting and positioning a layer of 15 nm-thick heavily doped n + (2.10 17 cm -3 ) into the 700nm-thick setback layer, we found that, when we positioned the n + layer 635 nm below the QW, the V TH shifted by only 37 mV and only a slight change of the subthreshold slope occurred, 3.12 mV/dec, for -2 V applied to the substrate