A Reliable Leakage Reduction Technique for Approximate Full Adder with Reduced Ground Bounce Noise (original) (raw)
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IJERT-Low Power CMOS Full Adder Design with Sleep Transistor for Submicron VLSI Technologies
International Journal of Engineering Research and Technology (IJERT), 2013
https://www.ijert.org/low-power-cmos-full-adder-design-with-sleep-transistor-for-submicron-vlsi-technologies https://www.ijert.org/research/low-power-cmos-full-adder-design-with-sleep-transistor-for-submicron-vlsi-technologies-IJERTV2IS110197.pdf Any computational circuit is incomplete without the use of an adder. Addition is one of the primary operations in arithmetic circuits. These adder cells commonly aimed to reduce power consumption and delay. These studies have also investigated different approaches realizing adders using CMOS technology. The designer's concern for the level of leakage current is mainly aimed at minimizing power dissipation. For portable electronic devices this equates to maximizing battery life. When a mobile phone is in standby mode, certain portions of the circuitry are shut down. Even though de-activated, these circuits have some leakage current flowing through them. Even if the leakage current is much smaller than the normal operating current of the circuit, it depletes the battery charge over the relatively long standby time, whereas the operating current during talk time only depletes the battery charge over the relatively short talk time. As a result, the leakage current has a disproportional effect on total battery life. In this project leakage power and the ground bounce noise is considerably reduced by the use of sleep transistor in full adder design. Size of the sleep transistor is determined by transistor resizing approach. 4 bit adder is implemented using 1 bit adder as reference. The simulation shows that, the 1 bit and 4 bit adders are efficient in terms of standby leakage power, active power and ground bounce noise. Simulations have been performed by using 130 nm CMOS. Electric Tool is used to design the schematic and layout level diagrams of our project. The LT-SPICE Tool will be used for simulation of the Spice code which tests the functionality of our generated layout and schematic blocks.
International Journal of Advanced Research in Electronics & Communication Engineering, 2012
Adder is the paramount circuit for many complex arithmetic operations. The adder cells mainly focus on reduction of power and increasing of speed. For mobile applications, designers work within a limited leakage power specification in order to meet good battery life. The designers apart from leveling of leakage current to ensure correct circuit operation also focuses on minimization of power dissipation. The power reduction must be achieved without comprising performance which makes it hard to reduce leakage current during normal operation of mobile. Power Gating is one such well known technique where a sleep transistor is added between actual ground rail and circuit ground. The device is turned off during sleep mode to cut-off the leakage path. This technique results in a substantial reduction in leakage at a minimal impact on performance. This paper will focus on reducing sub threshold leakage power consumption and ground bounce noise during the sleep to active mode transition. In the present paper we will propose low leakage 1 bit CMOS full adder circuit in 90nm technology with supply voltage of 1V. We will perform analysis and simulation of various parameters such as standby leakage power, active power, ground bounce noise and propagation delay using Cadence Spectre 90nm standard CMOS technology
Design and realisation of Low leakage 1-bit CMOS based Full Adder Cells for Mobile Applications
For the most recent CMOS feature sizes (e.g., 180nm), leakage power dissipation has become an overriding concern for VLSI circuit designers. As technology scales into the nano meter regime leakage power and noise immunity are becoming important metric of comparable importance to active power, delay and area for the analysis and design of complex arithmetic and logic circuits. In this project, low leakage 1-bit full adder cells are proposed for mobile applications. Noise immunity has been carefully considered since the significant threshold current of the low threshold voltage transition becomes more susceptible to noise. Since, Adders are heart of computational circuits and many complex arithmetic circuits are based on the addition. The vast use of this operation in arithmetic functions attracts a lot of researcher's attention to adder for mobile applications. In recent years, several variants of different logic styles have been proposed to implement 1-bit adder cells. Therefore a new transistor resizing approach for 1-bit full adder cells to determine the optimal sleep transistor size which reduce the leakage power has been proposed. The simulation results depicts that the proposed design also leads to efficient 1-bit full adder cells in terms of standby leakage power. In order to verify the leakage power, various designs of full adder circuits are simulated using DSCH, Micro wind and Virtuoso (Cadence).
A High-Level Technique for Estimation and Optimization of Leakage Power for Full Adder
International Journal of Nanoscience, 2013
Optimization of power is a very important issue in low-voltage and low-power application. In this paper, we have proposed power gating technique to reduce leakage current and leakage power of one-bit full adder. In this power gating technique, we use two sleep transistors i.e., PMOS and NMOS. PMOS sleep transistor is inserted between power supply and pull up network. And NMOS sleep transistor is inserted between pull down network and ground terminal. These sleep transistors (PMOS and NMOS) are turned on when the circuit is working in active mode. And sleep transistors (PMOS and NMOS) are turned off when circuit is working in standby mode. We have simulated one-bit full adder and compared with the power gating technique using cadence virtuoso tool in 45 nm technology at 0.7 V at 27°C. By applying this technique, we have reduced leakage current from 2.935 pA to 1.905 pA and leakage power from 25.04μw to 9.233μw. By using this technique, we have reduced leakage power up to 63.12%.
LOW-POWER 1-BIT FULL-ADDER CELL USING ENHANCED PASS TRANSISTOR LOGIC AND POWER GATING
Adders have become one of the important components in the digital world, such that there exists no design without it. Adders are not only used for additions, but it is also one of the basic building blocks that have been used for many other functions such as subtractions, multiplications, and divisions etc. In the field of Very Large Scale Integration (VLSI), Adders are used as the basic component from processors to ASICs. Propagation delay, Power and Area are the acceptable Quality metrics of the designed products. Recent days has proved that the use of Complementary Pass Transistor Logic (CPL) and sleep transistor provides a drastic reduction in the power compared to CMOS logic. Power Gating is one such well known technique where a sleep transistor is added between actual ground rail and circuit ground. The device is turned off during sleep mode to cut-off the leakage path. This technique results in a substantial reduction in leakage at a minimal impact on performance. This paper has spread the focus on Low power Adder design based on PTLs, with reduced sub threshold leakage power consumption and ground bounce noise during sleep to active mode transition, thereby achieving 2.5% reduction in power without affecting other quality metrics of the design. The CPL design has been modeled and analyzed using TANNER EDA with TSMC MOSIS 250nm technology. In the present paper we will propose low leakage 1 bit CMOS full adder circuit in 90nm technology with supply voltage of 1V. Keywords: CPL, Power, VLSI, Adder
Leakage Reduction Methodology in CMOS for the Design of 1-Bit Full Adder
International Journal of Engineering Technology and Management Sciences, 2021
This paper presents low leakage and high speed 1-bit full adder projected with low threshold NMOS transistors in associations with universal logic gates which leads to have reduced power and delay. The customized NAND and NOR gates, a necessary blocks, are presented to design a proposed adder cell. The simulations for the designed circuits performed in cadence virtuoso tool with 65 nm CMOS technology at a supply voltage of 1 Volts. The proposed universal gates and 1-bit adder cell is compared with conventional NAND/NOR gates and 1-bit adder. The proposed adder schemes with modified universal logic gates achieve significant saving in terms of delay which are more than 24% and which is at the cost of 5% when compared with conventional designs.
Design And Analysis Of Low Power High Performance Single Bit Full Adder
Adder is the significant circuit in arithmetic operations. Adder cells are designed for power and delay reduction. Now ground bounce noise is also necessary for good performance. In this paper the full adder is designed using only 8 Transistors using Pass Transistor Logic (PTL). The power gating technique is one such a best technique which reduces leakage power through the ground. This technique is implemented using sleep transistor added between ground rail and actual ground. Here a single bit 8 Transistor full adder is proposed. We will perform analysis and simulation of various parameters like power, delay and ground bounce noise using tanner EDA tool 180nm CMOS Technology.
ANALYSIS OF LOW POWER 32-BIT BRENT KUNG ADDER WITH GROUND BOUNCEING NOISE OPTIMIZATION
Reducing power dissipation is one of the most important issues in deeply scaled technology. Sub-threshold leakage currents to become a large component of total power dissipation with the scaling of technology. Multi–Threshold (MTCMOS) technique is a promising way to reduce leakage power consumption of the circuits but it gives a problem called ground bouncing noise which reduces the reliability of the circuit. Ground bouncing noise produced during sleep to active mode transitions is an important challenge in Multi-Threshold CMOS circuits. The noise aware techniques Trimode, Stacking and Gated ground with variable Sleep transistor size MTCMOS circuit are applies to a prototype 32 bit Brent Kung adder to optimize the ground bouncing noise, Current surges and power consumption is presented in this paper. Simulate and analyze the results by using Cadence Virtuoso at 90nm technology node and comparative analysis of their performance is done with variation in supply voltage (VDD).
Design and analysis of low run-time leakage in a 10 Transistors full adder in 45nm technology
2016 IEEE Region 10 Conference (TENCON), 2016
In this paper a new full adder is proposed. The number of Transistors used in the proposed full adder is 13.Average leakage is 62% of conventional 28 transistor CMOS full adder. The leakage power reduction results in overall power reduction. The proposed full adder is evaluated by virtuoso simulation software using 45 nm technology of cadence tools.
DESIGN OF LOW-POWER FULL ADDER IN 0.18 µm CMOS TECHNOLOGY
With the increase in device integration level and the growth in complexity of Integrated circuits, small delay and low power dissipation become important parameters as these increases performance and portability. Battery storage is limited, to extend battery life; low power operation is the primary requirement in integrated circuits. Furthermore, high speed and multiple parallel applications need high computing power, placing greater demands on energy storage elements within the system. Large power dissipation in high performance digital systems requires large size heat sinks. These off chip component makes chip bulky and require large space. Secondly, extra heat in integrated circuit degrades the system performance. The full adder (FA) is a very important and basic building block in Arithmetic and Logic unit (ALU) of digital processor. The most widely accepted metrics to measure the quality of a digital circuit or to compare various circuit styles is power delay product. Further, Portability imposes a strict limitation on power dissipation while needs more computational speeds. The reduced power consumption and the improved speed require optimizations at all levels of the design procedure.