Design and analysis of low run-time leakage in a 10 Transistors full adder in 45nm technology (original) (raw)
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In microprocessor and digital signal processor, Full Adder performs addition and therefore it is used for arithmetic operation and is also used for comparison and access the address in memory. For highly efficient operation of low powered and battery operated portable devices, Full adder is implemented using different structures. There is a 1-bit full adder using10 transistors are proposed in this paper. There are two techniques 1) power gating technique and 2) SVL (switch controllable voltage level) technique are proposed for reducing leakage current. The results based on power gating technique and SVL technique show that leakage current of 10 transistors based1-bit Full Adder are reduced to a large extent. For ten transistors based 1-bit Full Adder, delay is also reduced as compare to conventional full adder. All simulation results for leakage current and delay are performed with 45nm CMOS technology, 20ns access time and 0.05GHZ frequency using cadence virtuoso tool.
A High-Level Technique for Estimation and Optimization of Leakage Power for Full Adder
International Journal of Nanoscience, 2013
Optimization of power is a very important issue in low-voltage and low-power application. In this paper, we have proposed power gating technique to reduce leakage current and leakage power of one-bit full adder. In this power gating technique, we use two sleep transistors i.e., PMOS and NMOS. PMOS sleep transistor is inserted between power supply and pull up network. And NMOS sleep transistor is inserted between pull down network and ground terminal. These sleep transistors (PMOS and NMOS) are turned on when the circuit is working in active mode. And sleep transistors (PMOS and NMOS) are turned off when circuit is working in standby mode. We have simulated one-bit full adder and compared with the power gating technique using cadence virtuoso tool in 45 nm technology at 0.7 V at 27°C. By applying this technique, we have reduced leakage current from 2.935 pA to 1.905 pA and leakage power from 25.04μw to 9.233μw. By using this technique, we have reduced leakage power up to 63.12%.
Low Power and High Performance Full Adder in Deep Submicron Technology
2014
The leakage power dissipation problem of electronics systems has attracted a lot of attention from engineers and researchers over the years. Increasing leakage current in deep-sub micrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This work presents the performance of different full adders in deep-submicron using 45nnm, 65nm and 90nm technology. Finally, the paper explores different circuit techniques to estimate the leakage power consumption has been presented. An illustrative example has been provided to demonstrate the design and simulation of CMOS with various technologies using DSCH and MICROWIND program.
Leakage Reduction Methodology in CMOS for the Design of 1-Bit Full Adder
International Journal of Engineering Technology and Management Sciences, 2021
This paper presents low leakage and high speed 1-bit full adder projected with low threshold NMOS transistors in associations with universal logic gates which leads to have reduced power and delay. The customized NAND and NOR gates, a necessary blocks, are presented to design a proposed adder cell. The simulations for the designed circuits performed in cadence virtuoso tool with 65 nm CMOS technology at a supply voltage of 1 Volts. The proposed universal gates and 1-bit adder cell is compared with conventional NAND/NOR gates and 1-bit adder. The proposed adder schemes with modified universal logic gates achieve significant saving in terms of delay which are more than 24% and which is at the cost of 5% when compared with conventional designs.
A conventional Full Adder using 28 transistors is presented here. In digital signal processors and microprocessors, the Full Adder is not only important for addition based digital circuit like multiplier and divider but is also used for accessing the address in memory. For low power requirement, there is a need to reduce leakage current in Full Adder. In this paper SVL (self controllable voltage level) technique is introduced for leakage current reduction and then standby leakage power reduction. Using SVL technique we can provide DC voltage supply as per requirement for load circuit in active mode and decrease DC voltage supply for load circuit in standby mode. This paper represents that leakage current of Full Adder using SVL technique is reduced by 61.8% as conventional Full Adder at .7volt DC supply. Simulation result is performed with 45nm CMOS technology, 20ns access time and 0.05GHZ frequency using cadence virtuoso tool.
Design and realisation of Low leakage 1-bit CMOS based Full Adder Cells for Mobile Applications
For the most recent CMOS feature sizes (e.g., 180nm), leakage power dissipation has become an overriding concern for VLSI circuit designers. As technology scales into the nano meter regime leakage power and noise immunity are becoming important metric of comparable importance to active power, delay and area for the analysis and design of complex arithmetic and logic circuits. In this project, low leakage 1-bit full adder cells are proposed for mobile applications. Noise immunity has been carefully considered since the significant threshold current of the low threshold voltage transition becomes more susceptible to noise. Since, Adders are heart of computational circuits and many complex arithmetic circuits are based on the addition. The vast use of this operation in arithmetic functions attracts a lot of researcher's attention to adder for mobile applications. In recent years, several variants of different logic styles have been proposed to implement 1-bit adder cells. Therefore a new transistor resizing approach for 1-bit full adder cells to determine the optimal sleep transistor size which reduce the leakage power has been proposed. The simulation results depicts that the proposed design also leads to efficient 1-bit full adder cells in terms of standby leakage power. In order to verify the leakage power, various designs of full adder circuits are simulated using DSCH, Micro wind and Virtuoso (Cadence).
Optimized CMOS Design of Full Adder using 45nm Technology
This paper presents low power full adder designed with pass transistor logic which reduces the area , power and delay. we compared conventional 28T CMOS full adder with 16T and 8T full adder in terms of area , power and delay using 45um Technology
2013 Students Conference on Engineering and Systems (SCES), 2013
An overview of performance analysis and compression between various parameters of a low power high speed conventional 1-bit full adder has been presented here. The work elucidated here gives a quantitative comparison of the adder cell performance. This paper shows the advancement over active power, leakage current and delay. The comparative study based on a new logic approach, which reduces power consumption. With power supply of 0.7V, we have achieved reduction in active power consumption of 98.28nW and propagation delay of 0.737ns, which makes this circuit highly energy efficient. In this circuit we have reduced leakage current of 135.9nA. The designs have been carried out by virtuoso tool of cadence at 45nm technology.
Design and Simulation of Low Power 10T Full Adder using Cadence 16nM Technology
IJRASET, 2019
This paper presents the design of low voltage low power 10T full adder with minimum leakage power, and its transient analysis with cadence tools. Adder is the basic building block of Arithmetic in digital circuits, the area and power consumption of adder plays a vital role in portable devices. The low voltage low power full adder circuits are widely used in portable applications as it improves the battery lifetime. In this paper we have presented the design, simulation and comparative analysis of 27T and 10T full adder topologies with various supply voltages and lower technology node at Cadence Virtuoso TSMC 16nM technology.
PERFORMANCE ANALYSIS OF LOW POWER FULL ADDER CELLS USING 45NM CMOS TECHNOLOGY
International Journal of Microelectronics Engineering (IJME), 2015
This paper puts forward different low power adder cells using different XOR gate architectures. Adder plays an important role in arithmetic operation such as addition, subtraction, multiplication, division etc. The optimization and characterization of such low power adder designs will aid in comparison and choice of adder modules in system design. A comparative analysis is performed for the power, delay, and power delay product (PDP) optimization characteristic& deals with the design of five adder cells using transistors and schematic structure using CADENCE tool. 10 transistor adder circuits shows the least power consumption with others. Simulations are performed by using Cadence Design tools using 45nm CMOS technology. The four adder cell module proposed here demonstrates their advantages in comparison with Static Energy Recovery Full (SERF), including lower power consumption, smaller area, and higher speed at different frequencies. Keywords Low power, Static Energy Recovery Full Adder (SERF), 45 nm technology, power delay product (PDP).