Review of mixer design for low voltage - low power applications (original) (raw)
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A fully differential ultra low-voltage, ultra low-power down-conversion mixer is presented in this paper. The mixer is designed using four-terminal MOS transistors. The radio-frequency (RF) and local-oscillator signals are applied to the gate and bulk of the devices, respectively. The proposed circuit is designed and simulated in the TSMC 0.18_μm CMOS process, with a 1.9GHz RF signal; the simulation results show that the proposed mixer has a conversion gain of 8dB, IIP3 of -10.6dBm and SSB noise figure of 12.7dB. The total power consumption in the 0.5 V supply voltage is 1.32mW.
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A 65-NM CMOS RF Mixer for Different Applications
2015
A down conversion RF mixer is designed with 65nm CMOS technology for a different low power consumption applications. Mixer structure comprises a double-balanced Gilbert-Cell with improving linearity method in the RF stage of circuit; all is at a supply voltage of 1.8V and a power of 2.17 mW. The circuit is simulated for different spectrum applications as: 200 MHz mobile users, 1.9 GHz wireless applications, and 20 to 60 GHz commercial satellite and pointtopoint communications. The reported design achieves good values in terms of a radio frequency mixer evaluating parameters such as: Consumed Power, Conversion Gain, Noise Figure and Linearity.
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Microelectronics, Electromagnetics and Telecommunications, Volume 372, Lecture Notes in Electrical Engineering, pp 485-495, 2015
This paper discusses the design of a 2.4 GHz operated, ultra-low power CMOS down-converting active mixer based on double balanced Gilbert-cell resistor-loaded topology fabricated in standard 180 nm RF CMOS low-power technology. All the MOS transistors of the mixer core have ideally been biased to sub-threshold region. Consuming only 500 μW of DC power using 1.0 V supply and minimal LO power of −16 dBm, this mixer demonstrates a simulated power conversion gain of 17.2 dB with Double Side Band (DSB) noise figure of 13.3 dB. With the same DC power dissipation and LO power, −11.7 dBm IIP3 and −20.1 dBm 1-dB point have been obtained as discussed in the paper. Pre-layout and post layout simulation results match very well. The ultra-low power consumption of the proposed mixer due to subthreshold region of operation and lower local oscillator power are the advantages of this subthreshold mixer.
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CMOS Technology Dedicated to Low Power Consumption Wireless Applications
2014
The present work consists of designing a Single Balanced Mixer (SBM) with the 65 nm CMOS technology, this for a 1.9 GHz RF channel, dedicated to wireless applications. This paper shows; the polarization chosen for this structure, models of evaluating parameters of the mixer, then simulation of the circuit in 65nm CMOS technology and comparison with previously treated.
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