A Study on VLSI Physical Design Specific Issues (original) (raw)

Partitioning-based Methods for VLSI Placement

2008

The technique of using balanced min-cut partitioning in placement was presented by Breuer in 1977 [7]. Such min-cut placers use scalable and extensible divide-and-conquer algorithmic framework and tend to produce routable placements [9]. Recent work offers extensions to block placement and large-scale mixed-size placement [15, 18, 31], and robust incremental placement [33].

Ca & Sbo : A Novel Optimized Placement Algorithms for an Efficient Vlsi Design

Designing a simplest architecture involves appropriate placement, which is often, regarded as a critical concerns of physical design engineers. Placement and routing of chips in automated manner is been research since decades and provides better predictive performance than manual procedures. However, most of the automated models operating under meta-heuristic optimization fails in obtaining optimal solution due to premature convergence and non-optimal placement of solutions. In this paper, we develop a novel meta-heuristic optimization method namely Cellular Automata (CA) and Satin Bowerbird Optimization (SBO) that combines Primal-dual lagrangian technique (SimPL) and Complex Primal dual lagrangian (ComPL) for attaining optimal placement and routing of chips. The process of CA and SBO optimization approach operates on obtaining optimized placement solutions from the SimPL and ComPL solutions. The combination of CA-SimPL, SBO-SimPL, CA-ComPL and SBO-ComPL is implemented on electronic...

Progress and Challenges in VLSI Placement Research

2012

ABSTRACT Given the significance of placement in IC physical design, extensive research studies performed over the last 50 years addressed numerous aspects of global and detailed placement. The objectives and the constraints dominant in placement have been revised many times over, and continue to evolve. Additionally, the increasing scale of placement instances affects the algorithms of choice for high-performance tools.

Improving min-cut placement for VLSI using analytical techniques

2003

ABSTRACT Over the past few decades, several powerful placement algorithms have been used successfully in performing VLSI placement. With the increasing complexity of the VLSI chips, there is no clear dominant placement paradigm today. This work attempts to explore hybrid algorithms for large-scale VLSI placement. Our work aims to evaluate existing placement algorithms, estimate the ease of their reuse, and identify their sensitivities and limitations.

Perimeter Degree Technique for the Reduction of Routing Congestion during Placement in Physical Design of VLSI Circuits

Complexity

When used in conjunction with the current floorplan and the optimization technique in circuit design engineering, this research allows for the evaluation of design parameters that can be used to reduce congestion during integrated circuit fabrication. Testing the multiple alternative consequences of IC design will be extremely beneficial in this situation, as will be demonstrated further below. If the importance of placement and routing congestion concerns is underappreciated, the IC implementation may experience significant nonlinear problems throughout the process as a result of the underappreciation of placement and routing congestion concerns. The use of standard optimization techniques in integrated circuit design is not the most effective strategy when it comes to precisely estimating nonlinear aspects in the design of integrated circuits. To this end, advanced tools such as Xilinx VIVADO and the ICC2 have been developed, in addition to the ICC1 and VIRTUOSO, to explore for co...

A Degree-Based Clustering Technique for VLSI Placement

Journal of Algorithms & Computational Technology, 2009

In this paper, clustering for the circuit placement problem is examined from the perspective of wire length contribution from groups of nets. First, the final wire length data of groups of nets with different degrees are extracted and studied. It is illustrated that nets with high-degree contribute a high percentage to the total wire length. To remedy this problem, a clustering algorithm for placement is proposed that focuses on clustering nets with high-degree. This new clustering algorithm is implemented as a preprocessing step in the placement stage. ICCAD04 benchmark circuits abstracted from IBM are used to validate the placement quality by using four academic placers with and without the proposed preprocessing step. Experiments show that the overall placement results can be improved by up to 5%.