The role of custom design in ASIC Chips (original) (raw)

Closing the gap between ASIC and custom: An ASIC perspective

Kurt Keutzer

2000

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A methodology for custom VLSI layout

ANSHUL KUMAR

IEEE Transactions on Automatic Control, 1983

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Closing the gap between ASIC and custom

Kurt Keutzer

Proceedings of the 37th conference on Design automation - DAC '00, 2000

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ASIC chip synthesis

Gustavo Urena

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Full-custom vs. standard-cell design flow - an adder case study

Henrik Henriksson

2003

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Genetic Design Of VLSI-Layouts

Volker Schnecke

2000

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A Hierarchical Planning Tool for Custom VLSI Layout

Prakash C Rao

Computer Sciences Forum (Honeywell), 1984

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Developing an Integrated Design Strategy for Chip Layout Optimization

Juan Jauregui-becker

Electronic Markets

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An Optimized Power Performance and Area in ASIC Physical Design

Dr. Jami Venkata Suman

International Journal of Electronics, Electrical and Computational System, 2017

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ADVANTAGES AND CHALLENGES OF CUSTOM ASIC DEVELOPMENT FOR SPECIALIZED APPLICATIONS

IAEME Publication

IAEME PUBLICATION , 2024

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Using Chip Master Planning in Automatic ASIC Design Flow to Improve Performanceand Buffer Resource Management

Ali Jahanian

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An automatic clock tree design system for high-speed VLSI designs: planar clock routing with the treatment of obstacles

haksu kim

1999

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Integrated Circuit Conception: A Wire Optimization Technic Reducing Interconnection Delay in Advanced Technology Nodes

rachid ELGOURI

Electronics, 2017

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A flat, timing-driven design system for a high-performance CMOS processor chipset

Juergen Koehl

1998

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Design-Flow and Synthesis for ASICs: A Case Study

Patrizia Cavalloro

32nd Design Automation Conference, 1995

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Routing for analog chip designs at NXP semiconductors

M. van Den Akker

2011

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Full-Custom vs. Standard-Cell Design Flow – A Quantitative Adder Comparison

Đào Minh Thuấn

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The physical design of on-chip interconnections

Mary Lanzerotti

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2003

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Programmable Logic and Application Specific Integrated Circuits

Dave Landis

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Improvement of ASIC design processes

Vineet Sahula, C. Ravikumar

Design Automation Conference ASP-DAC 2002. IEEE 7th Asia and South Pacific and the IEEE 15th International Conference on VLSI Design, 2002

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Data-path layout design inside SOC

tong jing

IEEE 2002 International Conference on Communications, Circuits and Systems and West Sino Expositions

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ASIC by Design - Automated design of digital signal processing application-specific integrated circuits

D. Bouldin

IEEE Circuits and Devices Magazine, 2004

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Perimeter Degree Technique for the Reduction of Routing Congestion during Placement in Physical Design of VLSI Circuits

Mahammad Shafi

Complexity

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SANKEERNA: A LINEAR TIME, SYNTHESIS AND ROUTING AWARE, CONSTRUCTIVE VLSI PLACER TO ACHIEVE SYNERGISTIC DESIGN FLOW Copyright IJAET

IJAET Journal

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The impact of interconnect architecture on via-programmed structured ASICs (VPSAs)

Usman Ahmed

Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '10, 2010

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Concurrent Placement and Routing in the Design of Integrated Circuits

Adil Erzin

Automation and Remote Control, 2000

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Limitations and challenges of computer-aided design technology for CMOS VLSI

Kurt Keutzer

Proceedings of the IEEE, 2001

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Simultaneous Routing and Buffer Insertion algorithm for interconnect delay optimization in VLSI layout design

Mohamed Khalil-Hani

Microelectronics, 2008. ICM 2008. …, 2008

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ChipDesign: from theory to real world

Peter Pirsch

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Design methodology for semi custom processor cores

victor zyuban

Proceedins of the 14th ACM Great Lakes symposium on VLSI - GLSVLSI '04, 2004

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Pre-design consideration and evaluation for ASICs

M. Takla

[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit

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Closing the power gap between ASIC and custom

Kurt Keutzer

Proceedings of the 42nd annual conference on Design automation - DAC '05, 2005

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Circuit optimization using device layout motifs

Martin Trefzer

2014 5th European Workshop on CMOS Variability (VARI), 2014

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