Decoding of stochastically assembled nanoarrays (original) (raw)

Evaluation of Design Strategies for Stochastically Assembled Nanoarray Memories

A key challenge facing nanotechnologies is learning to control uncertainty introduced by stochastic self-assembly. In this article, we explore architectural and manufacturing strategies to cope with this uncertainty when assembling nanoarrays, crossbars composed of two orthogonal sets of parallel nanowires (NWs) that are differentiated at their time of manufacture. NW deposition is a stochastic process and the NW encodings present in an array cannot be known in advance. We explore the reliable construction of memories from stochastically assembled arrays. This is accomplished by describing several families of NW encodings and developing strategies to map external binary addresses onto internal NW encodings using programmable circuitry. We explore a variety of different mapping strategies and develop probabilistic methods of analysis. This is the first article that makes clear the wide range of choices that are available.

Nanowire Addressing with Randomized-Contact Decoders

Methods for assembling crossbars from nanowires (NWs) have been designed and implemented. Methods for controlling individual NWs within a crossbar have also been proposed, but implementation remains a challenge. A NW decoder is a device that controls many NWs with a much smaller number of lithographically produced mesoscale wires (MWs). Unlike traditional demultiplexers, all proposed NW decoders are assembled stochastically. In a randomized-contact decoder (RCD) [11], for example, field-effect transistors are randomly created at about half of the NW/MW junctions.

Nanowire Addressing in the Face of Uncertainty

IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06)

Exploiting the high-potential of nanoscale architectures requires that they be controlled by CMOS technology. Such an interface, a decoder, must control many nanowires (NWs) with a small number of meso-scale wires (MWs). Multiple types of decoder have been proposed, each of which can be modelled as embedding resistive switches in NWs. In this paper we present a general model for NW decoders and use it to specify the criteria they must meet to function correctly and be fault-tolerant. To illustrate the power of our model, we derive the first bounds on the size of a fault-tolerant randomized contact decoder.

A flexible simulation methodology and tool for nanoarray-based architectures

2010 IEEE International Conference on Computer Design, 2010

Nanoscale arrays based on nanowires are expected to have a promising future thanks to their amazing density and regularity. Experiments demonstrated the feasibility of this technology and pointed out that accurate reliability analyses should be accomplished to assure proper yield requirements. Due to the complexity of these systems and the arising necessity of thorough fault analysis, design automation tools are mandatory in order to explore architectural solutions and fault tolerant approaches deriving information from reliable nanoarray characterisation.

Defect tolerant probabilistic design paradigm for nanotechnologies

2004

Recent successes in the development and self-assembly of nanoelectronic devices suggest that the ability to manufacture dense nanofabrics is on the near horizon. However, the tremendous increase in device density of nanoelectronics will be accompanied by a substantial increase in hard and soft faults, posing a major challenge to current design methodologies and tools. In this paper we propose a novel probabilistic design paradigm for defective but reconfigurable nanofabrics. The new design goal is to devise an appropriate structural/behavioral decomposition which improves scalability by constraining the reconfiguration process, while meeting a desired probability of successful instantiation, i.e, yield. Our approach not only addresses the scalability problem in configuring dense nanofabrics subject to defects, but gives a rich framework in which critical trade-offs among performance, yield, and per chip cost can be explored. We present a concrete instance of the approach and show extensive experimental results supporting these claims.

RICE UNIVERSITY Programming the Nanocell, a Random Array of Molecules

The emerging field of molecular electronics seeks to create computational function from individual molecules or arrays of molecules. These nanoscale devices would then enable the production of faster, denser, cheaper computers. Clearly, there are many obstacles to building such devices, one of which is to develop methods for using lithographic wires to address molecules that are many orders of magnitude smaller in size. In this thesis, a moletronics design is presented that offers a method for connecting nanometer molecules to the world-at-large. This architecture involves the production of nanocells, or random arrays of molecules and metallic nanoparticles. The molecules have two discrete states and exhibit electrical behavior that enables complex logic in a nanocell. Methods are presented to take a random array of such switch states and alter them to program a nanocell as a useful logical device. Simulations of this programming process are presented and show that it is theoretically possible to obtain very high level function from these cells. Observations made during simulations are then used to formulate theorems about the programmability of nanocells. These theorems demonstrate that there is a dense solution space of molecular switch states that give rise to certain computation within a nanocell. Future directions of research, such as methods for wiring multiple nanocells together, are included as well.

Nanowire-based sublithographic programmable logic arrays

Symposium on Field Programmable Gate Arrays, 2004

How can Programmable Logic Arrays (PLAs) be built without relying on lithography to pattern their smallest features? In this paper, we detail designs which exploit emerging, bottom-up material synthesis techniques to build PLAs using molecular-scale nanowires. Our new designs accommodate technologies where the only post-fabrication programmable element is a non-restoring diode. We introduce stochastic techniques which allow us to restore the diode logic at the nanoscale so that it can be cascaded and interconnected for general logic evaluation. Under conservative assumptions using 10nm nanowires and 90nm lithographic support, we project yielded logic density around 500,000nm 2 /or term for a 60 or-term array; a complete 60-term, two-level PLA is roughly the same size as a single 4-LUT logic block in 22nm lithography. Each or term is comparable in area to a 4-transistor hardwired gate at 22nm. Mapping sample datapaths and conventional programmable logic benchmarks, we estimate that each 60-or-term PLA plane will provide equivalent logic to 5-10 4-input LUTs.

Limit on the Addressability of Fault-Tolerant Nanowire Decoders

IEEE Transactions on Computers, 2009

Although prone to fabrication error, the nanowire crossbar is a promising candidate component for next-generation nanometer-scale circuits. In the nanowire crossbar architecture, nanowires are addressed by controlling voltages on the mesowires. For area efficiency, we are interested in the maximum number of nanowires Nðm; eÞ that can be addressed by m mesowires in the face of up to e fabrication errors. Asymptotically tight bounds on Nðm; eÞ are established in this paper. In particular, it is shown that Nðm; eÞ ¼ Âð2 m =m eþ1=2 Þ. Interesting observations are made on the equivalence between this problem and the problem of constructing optimal error-correcting and all unidirectional error-detecting (EC/AUED) codes, superimposed distance codes, pooling designs, and diffbounded set systems. Results in this paper also improve upon those in the EC/AUED code literature.

Large-scale ordered 1D-nanomaterials arrays: Assembly or not?

Nano Today, 2013

One of the most difficult problems facing the integrated circuit industry is that conventional top-down strategies, which have been the methods of choice for decades, have almost reached their limit. With the industry quest for smaller electronic devices of higher functional complexity based on nano-technologies, which are faster, more portable and less energyconsuming, intensive efforts for solutions based on bottom-up strategies are currently invested. A major difficulty that challenges the creation of functional high-performance devices based on bottom-up grown nanostructures is the accurate deterministic positioning of the individual nanostructures into large perfectly aligned arrays, in a similar manner to top-down strategies. Two main approaches are chosen to solve these issues, involving post-growth assembly-based methods or grow-in-place assembly-free methods. This review provides an overview of the most recent developments in this field, with present perspective concerning their applicability as industrial processes, concentrating on the assembly of one-dimensional nanowires and nanotubes structures. Another route is devised that combines top-down and bottom-up strategies for the on-place NWs growth in a single step, exploiting the strengths of both approaches. Although major advance is shown in the field, it is concluded that current methods are still lacking on their way to become high throughput, industrial-scale manufacturable, and potentially can be covered by a hybrid approach, integrating top-down techniques with grow-in-place assembly-free growth methods.