An exercise on hardware/software codesign following the RISC model (original) (raw)

IJRRECS/August 2013/Volume-1/Issue-4/295-299 EFFECTIVE SYSTEM ARCHITECTURE BASED RISC STRATEGY

Embedded computers as well as personal computers have become the part and parcel of everyday human life. There is a rapid development in the computer structure. Several computers of different types are developed. Hence there is the deep need to introduce the architecture of the computer to everyone. Every engineer is supposed to know the best about computer. Also a strategy is now being developed to design the Intellectual Property core processors so that anyone could build his own computer/ embedded system as per his specific application. It is possible to build even reconfigurable processors so that the same processor can be reconfigured for different applications. Hence there is the deep need to develop the ability to build one's own processor to meet the needs of one's computing needs. This paper is such an attempt to introduce the RISC based design of processor for pedagogical purposes.

EFFECTIVE SYSTEM ARCHITECTURE BASED RISC STRATEGY

Embedded computers as well as personal computers have become the part and parcel of everyday human life. There is a rapid development in the computer structure. Several computers of different types are developed. Hence there is the deep need to introduce the architecture of the computer to everyone. Every engineer is supposed to know the best about computer. Also a strategy is now being developed to design the Intellectual Property core processors so that anyone could build his own computer/ embedded system as per his specific application. It is possible to build even reconfigurable processors so that the same processor can be reconfigured for different applications. Hence there is the deep need to develop the ability to build one’s own processor to meet the needs of one’s computing needs. This paper is such an attempt to introduce the RISC based design of processor for pedagogical purposes. This work introduces a processor that can perform all the general tasks such as addiction, subtraction, multiplication, division, AND, OR, XOR, NOT, load and store operations using logic based digital strategy. Embedded system design also becomes simple with the introduction of computer hardware for pedagogical purposes. Extensive testing has been carried out for testing the design and found to give accurate results. The processor is designed with Xilinx ISE 12.1 targeted for porting into the Spartan 6 FPGA kit. The design is quite synthesizable.

Risc Processor for Computer Hardware Introduction

International Journal of Modern Trends in Engineering and Research, 2015

Processors are the heart of all “smart” devices, whether they be electronic devices or otherwise. Their smartness comes as a direct result of the decisions and controls that processor makes.The existing commercial microprocessors are provided as black box units; with which users are unable to monitor internal signals and operation process, neither can they modify the original structure. In order to solve this problem 16-bit fully functional single cycle processor is designed in terms of its architecture and its functional capabilities. The procedure of design and verification for a 16-bit processor is introduced in this paper. The key architecture elements are being described, as well as the hardware block diagram and internal structure. The summary of instruction set is presented. This processor is modify as a VERILOG Hardware Description Language (VERILOGHDL) and gives access to every internal signal. In order to consume fewer resources, the design of arithmetic logical unit (ALU)...

The survey of concepts of architecture in RISC and CISC computers

IJARIIT, 2018

In the ever-growing world of computer architecture, Instruction Set Architecture (ISA) is one of the major components of a computer system, as it provides the information about the instructions present in the system prior to the programmer. Having various implementations and uses it is classified into various categories, RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer) being two, both being a bit different in their basic architecture and working. Both CISC and RISC architectures continue to be widely used. The research topic on CISC and RISC has been a well-known research area for many years. Since modern processors have to address both power consumption and performance, it is important to compare these architectures to support future project decisions. Our paper also includes basic details regarding the various addressing modes, instruction formats along with the instruction execution cycle giving detailed information about RISC and CISC processors simultaneously.

A software oriented approach to hardware/software codesign

1994

We present a software oriented approach to hardware/software codesign by applying traditional compiler techniques to the hardware/software partitioning problem and linking a compiler to a state of the art hardware synthesis technology. The system is specified in C or C++. Time critical regions are identified by means of profiling and are automatically implemented in user programmable logic with high level and logic synthesis design tools. The underlying architecture is an add-on board with user programmable logic, connected to a Sparc based workstation via the system bus. We present a novel partitioning technique based on a hierarchical candidate preselection scheme, that utilizes profilers and estimators for performance and cost. Our approach allows (a) efficient collection of profiling data due to the usage of C and C++ as specification languages, (b) fast partitioning due to a candidate preselection scheme, and (c) high complexity of the hardware partition due to a logic emulation system.

HARPO/L: A language for hardware/software codesign

Newfoundland Electrical and …, 2008

Advances in digital hardware densities make it feasible to im-plement large portions of applications on Application Spe-cific Integrated Circuits (ASIC) or programmable hardware such as Field Programmable Gate Arrays (FPGA) and Coarse Grained Reconfigurable Architectures ( ...

Comparative Study of RISC Architectures

2011

RISC or Reduced Instruction Set Computer is a design architecture that focuses on simplification of the instruction set to achieve the goal of a simplified architecture implementation. It is characterized by certain distinguishing features such as single cycle execution time, simplified instruction set and load/store architecture. However, new generation RISC processors are modifying some of these features, while adding more attributes based on their areas of application. The current paper reviews some of the RISC architectures seen over the years and analyzes their salient features. RISC( Reduced Instruction Set Computer) was first conceptualized at the university of California, Berkely with the aim of developing a single-chip computer with a simplified instruction set, as opposed to the CISC (Complex Instruction Set Computer) architecture that was prevalent at the time. The motivation behind the development of RISC was to avoid consequences that accompanied the complex architectur...