An exercise on hardware/software codesign following the RISC model (original) (raw)

IJRRECS/August 2013/Volume-1/Issue-4/295-299 EFFECTIVE SYSTEM ARCHITECTURE BASED RISC STRATEGY

EFFECTIVE SYSTEM ARCHITECTURE BASED RISC STRATEGY

Embedded computers as well as personal computers have become the part and parcel of everyday human life. There is a rapid development in the computer structure. Several computers of different types are developed. Hence there is the deep need to introduce the architecture of the computer to everyone. Every engineer is supposed to know the best about computer. Also a strategy is now being developed to design the Intellectual Property core processors so that anyone could build his own computer/ embedded system as per his specific application. It is possible to build even reconfigurable processors so that the same processor can be reconfigured for different applications. Hence there is the deep need to develop the ability to build one’s own processor to meet the needs of one’s computing needs. This paper is such an attempt to introduce the RISC based design of processor for pedagogical purposes. This work introduces a processor that can perform all the general tasks such as addiction, subtraction, multiplication, division, AND, OR, XOR, NOT, load and store operations using logic based digital strategy. Embedded system design also becomes simple with the introduction of computer hardware for pedagogical purposes. Extensive testing has been carried out for testing the design and found to give accurate results. The processor is designed with Xilinx ISE 12.1 targeted for porting into the Spartan 6 FPGA kit. The design is quite synthesizable.

Risc Processor for Computer Hardware Introduction

International Journal of Modern Trends in Engineering and Research, 2015

Processors are the heart of all “smart” devices, whether they be electronic devices or otherwise. Their smartness comes as a direct result of the decisions and controls that processor makes.The existing commercial microprocessors are provided as black box units; with which users are unable to monitor internal signals and operation process, neither can they modify the original structure. In order to solve this problem 16-bit fully functional single cycle processor is designed in terms of its architecture and its functional capabilities. The procedure of design and verification for a 16-bit processor is introduced in this paper. The key architecture elements are being described, as well as the hardware block diagram and internal structure. The summary of instruction set is presented. This processor is modify as a VERILOG Hardware Description Language (VERILOGHDL) and gives access to every internal signal. In order to consume fewer resources, the design of arithmetic logical unit (ALU)...

The survey of concepts of architecture in RISC and CISC computers

IJARIIT, 2018

In the ever-growing world of computer architecture, Instruction Set Architecture (ISA) is one of the major components of a computer system, as it provides the information about the instructions present in the system prior to the programmer. Having various implementations and uses it is classified into various categories, RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer) being two, both being a bit different in their basic architecture and working. Both CISC and RISC architectures continue to be widely used. The research topic on CISC and RISC has been a well-known research area for many years. Since modern processors have to address both power consumption and performance, it is important to compare these architectures to support future project decisions. Our paper also includes basic details regarding the various addressing modes, instruction formats along with the instruction execution cycle giving detailed information about RISC and CISC processors simultaneously.

A software oriented approach to hardware/software codesign

1994

We present a software oriented approach to hardware/software codesign by applying traditional compiler techniques to the hardware/software partitioning problem and linking a compiler to a state of the art hardware synthesis technology. The system is specified in C or C++. Time critical regions are identified by means of profiling and are automatically implemented in user programmable logic with high level and logic synthesis design tools. The underlying architecture is an add-on board with user programmable logic, connected to a Sparc based workstation via the system bus. We present a novel partitioning technique based on a hierarchical candidate preselection scheme, that utilizes profilers and estimators for performance and cost. Our approach allows (a) efficient collection of profiling data due to the usage of C and C++ as specification languages, (b) fast partitioning due to a candidate preselection scheme, and (c) high complexity of the hardware partition due to a logic emulation system.

HARPO/L: A language for hardware/software codesign

Newfoundland Electrical and …, 2008

Advances in digital hardware densities make it feasible to im-plement large portions of applications on Application Spe-cific Integrated Circuits (ASIC) or programmable hardware such as Field Programmable Gate Arrays (FPGA) and Coarse Grained Reconfigurable Architectures ( ...

Comparative Study of RISC Architectures

2011

RISC or Reduced Instruction Set Computer is a design architecture that focuses on simplification of the instruction set to achieve the goal of a simplified architecture implementation. It is characterized by certain distinguishing features such as single cycle execution time, simplified instruction set and load/store architecture. However, new generation RISC processors are modifying some of these features, while adding more attributes based on their areas of application. The current paper reviews some of the RISC architectures seen over the years and analyzes their salient features. RISC( Reduced Instruction Set Computer) was first conceptualized at the university of California, Berkely with the aim of developing a single-chip computer with a simplified instruction set, as opposed to the CISC (Complex Instruction Set Computer) architecture that was prevalent at the time. The motivation behind the development of RISC was to avoid consequences that accompanied the complex architectur...

A Computer Architecture Educational System based on a 32-bit RISC Processor

This paper describes the implementation of a system-on-a-programmable-chip (SOPC) development board to support computer architecture laboratories at a low cost. A commercial fieldprogrammable-gate-array (FPGA) was employed to develop our reduced-instruction-set-computer (RISC) soft processor core that may be programmed through a user-friendly environment accompanied by an assembler. Our approach aims to support a wide variety of student projects in our engineering curriculum, increase students productivity and decrease the development time. Through our implementation, students are introduced to RISC architecture concepts, SOPC design and structure of assemblers. The reusability of the hardware permits the materialization of future projects according to our educational needs. The proposed inexpensive solution is a complete educational environment suitable for undergraduate use.

Reconfigurable Model for RISC Processors

2016

The instruction set of a processor is embodied in the particular micro-architecture representing the processor hardware. Verifying proper operation of the instruction set for a particular processor hardware implementation requires exhaustive testing to expose unknown dependencies and other elusive design flaws. This paper presents the research and development of a flexible micro-architectural model written in SystemC for a RISC processor based upon a user defined configuration database; the RISC processor is based on an architecture assigned in course Design of Computer Systems (DCS) offered at Rochester Institute of Technology (RIT). This model will be tested by a test bench written in SystemVerilog, using randomly generated instructions, and results will be compared with various DCS student processors originally developed at the Register Transfer Level (RTL) in a Hardware Description Language (HDL) such as Verilog or VHDL. The test bench will provide stimulus such as the system cl...

Design of RISC Processor Using VHDL and Cadence

Advanced Techniques in Computing Sciences and Software Engineering, 2009

The project deals about development of a basic RISC processor. The processor is designed with basic architecture consisting of internal modules like clock generator, memory, program counter, instruction register, accumulator, arithmetic and logic unit and decoder. This processor is mainly used for simple general purpose like arithmetic operations and which can be further developed for general purpose processor by increasing the size of the instruction register. The processor is designed in VHDL by using Xilinx 8.1i version. The present project also serves as an application of the knowledge gained from past studies of the PSpice program. The study will show how PSpice can be used to simplify massive complex circuits designed in VHDL Synthesis. The purpose of the project is to explore the designed RISC model piece by piece, examine and understand the Input/ Output pins, and to show how the VHDL synthesis code can be converted to a simplified PSpice model. The project will also serve as a collection of various research materials about the pieces of the circuit.

Design of a 16-bit RISC Processor Using VHDL

International Journal of Engineering Research and, 2017

This paper targets the design and implementation of a 16-bit RISC Processor using VHDL (Very High Speed Integrated Circuit Hardware Description Language). As IC chip design involves complex computations and intense usage of resources, by using an HDL we can save resources and time by implementing it using the software approach. The implementation strategies have been borrowed from the popular MIPS architecture to a certain extent. The processor has 16-bit arithmetic and logical instruction set which has been designed and simulated. The instruction set is extremely simple and it gives an insight into the kind of hardware that would be required to execute the instructions accordingly. The ALU, instruction register, program counter, register file, control unit and memory have been integrated in the proposed processor. All the modules in the design are coded in VHDL to ease the description, verification, simulation and hardware implementation. The blocks are designed using the behavioral approach.

A Study of Hardware Programming from a Compilation Perspective

2005

I propose a systematic review and evaluation of the use of general purpose, high-level programming languages for the design and synthesis of circuit specifications that implement algorithms directly as specialized hardware configurations. Specifically, I propose an examination of the, so-called, semantic gap between the understood features and semantics of popular software programming languages such as C and C++, and the capabilities of programmable logic devices such as FPGAs. A significant amount of research effort has already been devoted to this topic, but it is my belief that this research has generally failed to adequately address certain key issues in both principle and implementation. My research will comprise a study of the theory and practice of programming hardware descriptions, with the aim of providing insights that suggest how to bridge the semantic gap and yield more effective hardware programming techniques.

A Logic-Based Approach for Hardware/Software Codesign

2000

In the hardware industry, simulation is still all too frequently considered synonymous with verification. The design process usually consists of developing an implementation from a specification without the use of any formal proof techniques. Both are then simulated for a number of inputs (an approach known as co-simulation [1]). Bugs discovered are removed and the simulation process is repeated over again. However, formal verification cannot completely replace the existing simulation approach.

Hardware-software codesign of embedded systems

1994

Abstract Designers generally implement embedded controllers for reactive real-time applications as mixed software-hardware systems. In our formal methodology for specifying, modeling, automatically synthesizing, and verifying such systems, design takes place within a unified framework that prejudices neither hardware nor software implementation. After interactive partitioning, this approach automatically synthesizes the entire design, including hardware-software interfaces.

A codesign back-end approach for embedded system design

ACM Transactions on Design Automation of Electronic Systems, 2000

Continuous advances in processor and ASIC technologies enable the integration of more and more complex embedded systems. Since their implementations generally require the use of heterogeneous resources (e.g., processor cores, ASICs) in one system with stringent design constraints, the importance of hardware/software codesign methodologies increases steadily. Interfacing heterogeneous hardware and software components together through a communication structure is particularly error prone and time consuming. Hence, on the basis of a generic architecture dedicated to telecommunication and multimedia applications, we propose an extended communication synthesis method that provides characterization of communications and their implementation schemes in the target architecture. This method takes place after the partitioning and scheduling phase and may constitute the basis of a back-end of a codesign framework leading to HW/SW integration.