Design of efficient reversible floating-point arithmetic unit on field programmable gate array platform and its performance analysis (original) (raw)
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IRJET, 2021
Reversible logic is a promising field of research that finds applications in low power computing, quantum computing, optical computing, and other emerging technologies. A floating-point unit (FPU) is a part of a computer system specially designed to carry out operations on floating point numbers. In this paper an arithmetic unit based on IEEE-754 standard for floating point numbers has been implemented on FPGA Board. Here Floating Point Unit (FPU) follows IEEE single precision format. Various arithmetic operations such as, addition, subtraction multiplication division, square root and bit shifting on floating point numbers have been performed on arithmetic unit.
International Journal of Electrical and Computer Engineering (IJECE), 2023
Most modern computer applications use reversible logic gates to solve power dissipation issues. This manuscript uses an efficient multi-functional reversible arithmetic and logical unit (MF-RALU) to perform 30 operations. The 32-bit MF-RALU includes arithmetic, logical, complement, shifters, multiplexers, different adders, and multipliers. The multi-bit reversible multiplexers are used to construct the MF-RALU structure. The Reduced instruction set computer (RISC) processor is designed to realize the functionality of the MF-RALU. The MF-RALU can perform its operation in a single clock cycle. The 1-bit RALU is developed and compared with existing approaches with improvements in performance metrics. The 32-bit reversible arithmetic units (RAUs) and reversible logical units (RLUs) are constructed using 1-bit RALU. The MF-RALU and RISC processor are synthesized individually in the Vivado environment using Verilog-HDL and implemented on Artix-7 field programmable gate array (FPGA). The MF-RALU utilizes a <11% chip area and consumes 332 mW total power. The RISC processor utilizes a <3% chip area and works at 483 MHZ frequency by consuming 159 mW of total power on Artix-7 FPGA.
International Journal of Electrical and Computer Engineering (IJECE)
Most modern computer applications use reversible logic gates to solve power dissipation issues. This manuscript uses an efficient multi-functional reversible arithmetic and logical unit (MF-RALU) to perform 30 operations. The 32-bit MF-RALU includes arithmetic, logical, complement, shifters, multiplexers, different adders, and multipliers. The multi-bit reversible multiplexers are used to construct the MF-RALU structure. The Reduced instruction set computer (RISC) processor is designed to realize the functionality of the MF-RALU. The MF-RALU can perform its operation in a single clock cycle. The 1-bit RALU is developed and compared with existing approaches with improvements in performance metrics. The 32-bit reversible arithmetic units (RAUs) and reversible logical units (RLUs) are constructed using 1-bit RALU. The MF-RALU and RISC processor are synthesized individually in the Vivado environment using Verilog-HDL and implemented on Artix-7 field programmable gate array (FPGA). The M...
FPGA IMPLEMENTATION ON REVERSIBLE FLOATING POINT MULTIPLIER
Field programmable gate arrays (FPGA) are increasingly being used in the high performance and scientific computing community to implement floating-point based system. The reversible single precision floating point multiplier (RSPFPM) requires the design of reversible integer multiplier (2424) based on operand decomposition approach. Reversible logic is used to reduce the power dissipation than classical logic and do not loss the information bit which finds application in low power computing, quantum computing, optical computing, and other emerging computing technologies. Among the reversible logic gates, Peres gate is utilized to design the multiplier since it has lower quantum cost. Operands of the multiplier is decomposed into three partitions of 8 bits each using operand decomposition method. Thus the 2424 bit reversible multiplication is performed through nine reversible 8x8 bit multipliers and output is summed to yield an efficient multiplier optimized in terms of quantum cost, delay, and garbage outputs. This proposed work is designed and developed in the VHSIC hardware description language (VHDL) code and simulation is done using Xilinx 9.1simulation tool.
IJERT-Design and Analysis of Low Power Reversible Adder/Subtractor Circuits
International Journal of Engineering Research and Technology (IJERT), 2020
https://www.ijert.org/design-and-analysis-of-low-power-reversible-adder-subtractor-circuits https://www.ijert.org/research/design-and-analysis-of-low-power-reversible-adder-subtractor-circuits-IJERTV9IS090366.pdf In recent years, reversible logic has become a promising technology in the areas of low power VLSI design, nanotechnology, quantum computing and optical computing. The performance and reliability of digital systems which are now implemented using conventional logic gates can be enhanced by the usage of reversible logic gates, which pave for low power consumption and lesser quantum delays, thus increasing the speed of computation. Adder/subtractor circuits form the fundamental block in the arithmetic and logic unit of processors and other digital logic programmable devices. The performance of a digital system, its speed and throughput depend critically on the way these circuits are designed. Adder circuits are used in the Graphics Processing Unit(GPU) of computers for graphics applications to reduce complexity. Any way to enhance the performance and computational speed of these circuits will pave way for a better ALU. Incorporating the concepts of reversible computing in the design of adder/subtractor circuits can significantly enhance the performance and speed of operation of digital systems. In this paper, two existing adder/subtractor designs and a novel design are compared, analyzed for different bit lengths (1,8,16,32,64). Detailed analysis of reversible logic design parameters, power consumption parameters, and FPGA utilization parameters is carried out. These designs are analyzed and simulated using the Xilinx Vivado tool and implemented on Zedboard Zynq 7000 Evaluation and Development kit(xc7z020clg484-1). The proposed design outperforms the existing designs.
Design and Implementation of Optimized 32-Bit Reversible Arithmetic Logic Unit
With the growing advent of VLSI technology, the device size is shrinking and the complexity of the circuit is increasing exponentially. Power dissipation is considered as one of the most important design parameter. Reversible logic is an emerging and promising technology that provides almost zero power dissipation. Power consumption is also considered as an important parameter in digital circuits. In this paper, an efficient fault tolerant 32-bit reversible arithmetic and logic unit is designed and implemented using some parity preserving gates. The proposed design is better in terms of quantum cost and power dissipation. The number of garbage outputs are reduced by using them as an arithmetic or logical operation. The design can perform three arithmetic operations: Adder, Subtractor, Multiplier and four logical operations: Transfer A, Transfer B, Bitwise AND, XOR operation. The results of the proposed design are then compared with the existing design.
Design and FPGA Implementation of a Low Power Arithmetic Logic Unit
Arithmetic logic unit is the core of any CPU that can be part of a programmable reversible computing device such as a quantum computer. The major concern for ALU design ,using normal gates is heavy power consumption. The main reason for power consumption is the normal irreversible gates. In order to ensure low power design constraint a new type of gates called reversible gates were introduced. In reversible gates the number of inputs is equal to the number of outputs and there is a one to one mapping between the inputs and outputs. Here in this paper we discuss the design of a low power ALU using reversible gates and its implementation on FPGA.
Design of a Reversible Floating-Point Adder Architecture
—The study of reversible circuits holds great promise for emerging technologies. Reversible circuits offer the possibility for great reductions in power consumption, and quantum computers will require logically reversible digital circuits. Many different reversible implementations of logical and arithmetic units have been proposed in the literature, but very few reversible floating-point designs exist. Floating-point operations are needed very frequently in nearly all computing disciplines, and studies have shown floating-point addition to be the most oft used floating-point operation. In this paper we present for the first time a reversible floating-point adder that closely follows the IEEE754 specification for binary floating-point arithmetic. Our design requires reversible designs of a controlled swap unit, a subtracter, an alignment unit, signed integer representation conversion units, an integer adder, a normalization unit, and a rounding unit. We analyze these major components in terms of quantum cost, garbage outputs, and constant inputs.
Novel Reversible Variable Precision Multiplier Using Reversible Logic Gates
Journal of Computer Science
Multipliers play a vital role in digital systems especially in digital processors. There are many algorithms and designs were proposed in the earlier works, but still there is a need and a greater interest in designing a less complex, low power consuming, fastest multipliers. Reversible logic design became the promising technologies gaining greater interest due to less dissipation of heat and low power consumption. In this study a reversible logic gate based design of variable precision multiplier is proposed which have the greater efficiency in power consumption and speed since the partial products received are accumulated as soon as they are computed which results reduction in the need of memory.