Charged Particle Tracking in Real-Time Using a Full-Mesh Data Delivery Architecture and Associative Memory Techniques (original) (raw)
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The AMchip is a VLSI device that implements the Associative Memory function, a special content addressable memory specifically designed for high energy physics applications and first used in the CDF experiment at Tevatron. The 4th generation of AMchip has been developed for the core pattern recognition stage of the Fast TracKer (FTK) processor: a hardware processor for online reconstruction of particle trajectories at the ATLAS experiment at LHC. We present the architecture, design considerations, power consumption and performance measurements of the 4th generation of AMchip. We present also the design innovations toward the 5th generation and the first prototype results.
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The Fast TracKer (FTK) is an extremely powerful and very compact processing unit, essential for efficient Level 2 trigger selection in future high-energy physics experiments at the LHC. FTK employs Associative Memories (AM) to perform pattern recognition; input and output data are transmitted over serial links at 2 Gbit/s to reduce routing congestion at the board level. Prototypes of the AM chip and of the AM board have been manufactured and tested, in preparation of the imminent design of the final version.
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We propose precise and fast-track reconstruction at hadron collider experiments, for use in online trigger decisions. We describe the features of fast-track (FTK), a highly parallel processor dedicated to the efficient execution of a fast-tracking algorithm. The hardware-dedicated structure optimizes speed and size; these parameters are evaluated for the ATLAS experiment. We discuss some applications of high-quality tracks available to the trigger logic at an early stage, by using the LHC environment as a benchmark. The most interesting application is online selection of b-quarks down to very low transverse momentum, providing interesting hadronic samples: examples are , potentially useful for jet calibration, and multi-b final states for supersymmetric Higgs searches. The paper is generated from outside the ATLAS experiment and has not been discussed by the ATLAS collaboration.
Nuclear Instruments & Methods in Physics Research Section A-accelerators Spectrometers Detectors and Associated Equipment, 1995
The future Large Hadron Collider (LHC), to be built at CERN, presents among other technological challenges a formidable problem of real-time data analysis. At a primary event rate of 40 MHz, a multi-stage trigger system has to analyze data to decide which is the fraction of events that should be preserved on permanent storage for further analysis. We report on implementations of local algorithms for feature extraction as part of triggering, using the detectors of the proposed ATLAS experiment as a model. The algorithms were implemented for a decision frequency of 100 kHz, on different data-driven programmable devices based on structures of field-programmable gate arrays and memories. The implementations were demonstrated at full speed with emulated input, and were also integrated into a prototype detector running in a test beam at CERN, in June 1994.
The future evolution of the Fast Tracker processing unit
2015 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2015
Real time tracking is a key ingredient for online event selection at hadron colliders. The Silicon Vertex Tracker at the CDF experiment and the Fast Tracker at ATLAS are two successful examples of the importance of dedicated hardware to reconstruct full events at hadron colliders. We present the future evolution of this technology, for applications to the High Luminosity runs at the Large Hadron Collider where Data processing speed will be achieved with custom VLSI pattern recognition and linearized track fitting executed inside modern FPGAs, exploiting deep pipelining, extensive parallelism, and efficient use of available resources. In the current system, one large FPGA executes track fitting in full resolution inside low resolution candidate tracks found by a set of custom ASIC devices, called Associative Memories. The FTK dual structure, based on the cooperation of VLSI AM and programmable FPGAs, will remain, but we plan to increase the FPGA parallelism by associating one FPGA to each AM chip. Implementing the two devices in a single package would achieve further performance improvements, plus miniaturization and integration of the state of the art prototypes. We present the new architecture, the design of the FPGA logic performing all the complementary functions of the pattern matching inside the AM, the tests performed on hardware
The Evolution of FTK, a Real-Time Tracker for Hadron Collider Experiments
Astroparticle, Particle and Space Physics, Detectors and Medical Physics Applications - Proceedings of the 11th Conference, 2010
We describe the architecture evolution of the highly-parallel dedicated processor FTK, which is driven by the simulation of LHC events at high luminosity (10 34 cm -2 s -1 ). FTK is able to provide precise on-line track reconstruction for future hadronic collider experiments. The processor, organized in a two-tiered pipelined architecture, execute very fast algorithms based on the use of a large bank of pre-stored patterns of trajectory points (first tier) in combination with full resolution track fitting to refine pattern recognition and to determine off-line quality track parameters. We describe here how the high luminosity simulation results have produced a new organization of the hardware inside the FTK processor core. *