High transconductance 0.1 mu m pMOSFET (original) (raw)
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Thorough characterization of deep-submicron surface and buried channel pMOSFETs
Solid-state Electronics, 2002
In this paper, the short channel effects in buried and surface channel pMOSFETs are studied. The effective channel length, threshold voltage, source-drain series resistance, carrier mobility in various temperature ranges and the draininduced-barrier-lowering effect are investigated. Hot carrier degradation is performed in order to extrapolate the device lifetimes and the maximum drain bias that can be applied. Low frequency noise measurements are also carried out in order to evaluate the impact of the gate doping type on the device noise performance. Ó
Solid-State Electronics, 2009
A detailed analysis of the body potential impact on the performance enhancement of BC pMOSFET when the body is not contacted, is reported in this paper. Investigations on floating-body device behavior reveal that these new floating body effect leads to pMOSFET drive capability increase with lower subthreshold slope, no Ioff degradation and no kink effect. The body potential is mainly governed by the ECB component between the partial n+ poly-gate and n type silicon substrate through the 1.6 nm thin gate oxide. Static characterizations of various layouts and geometries demonstrate that narrow pMOSFET and H gate design provide the highest Ion gain due to higher body potential. Furthermore, it has been found that the largest n+ poly gate area results in the fastest switch-on Id transients.
50 nm Vertical Replacement-Gate (VRG) pMOSFETs
International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138), 2000
We present the first p-channel Vertical Replacement-Gate (VRG) MOSFETs. Like the VRG-nMOSFETs demonstrated last year (1), these devices show promise as a successor to planar MOSFETs for highly-scaled ULSI. Our pMOSFETs retain the key features of the nMOSFETs and add channel doping by ion implantation and raised source/drain extensions (SDEs). We have significantly improved the core VRG process to provide high-performance devices with gate lengths of 100 nm and below. Since both sides of the device pillar drive in parallel, the drive current per µm of coded width can far exceed that of planar MOSFETs. Our 100 nm VRG-pMOSFETs with t OX = 25 Å drive 615 µA/µm at 1.5 V with I OFF = 8 nA/µm -80% more drive than specified in the 1999 ITRS Roadmap at the same I OFF . We demonstrate 50 nm VRG-pMOSFETs with t OX = 25 Å that approach the 1.0 V roadmap target of I ON = 350 µA/µm at I OFF = 20 nA/µm without the need for a hyperthin (< 20 Å) gate oxide.
Effect of Variation of Gate Work-Function on Electrical Characteristics of Lightly Doped PMOSFET
International Journal of Future Generation Communication and Networking, 2019
Miniaturization of the dimensions of Metal Oxide Semiconductor field effect (MOSFET) transistors is very requisite nowadays for the enhanced enactment and integrated circuit compactness but this step of scaling arises to complications such as increased gate resistance and high leakage current. The utilization of integrated circuits in high-performance electronic gadgets is increasing day by day. As more and more complex functions are required in various fields like data/image processing and wired/wireless communication, the need to incorporate these functions in a compact package is also increasing. The reduction of channel length and other reduced parameters blemishes the device performance. The initial design can be designed and virtually fabricated in Computer-aided design (CAD) tool and the complexities of the design can be analysed at the early stage before the actual fabrication is done in fabrication laboratories. The scaling down of device dimensions results in a drastic increase in the sub-threshold leakage current of the device. There are various ways to reduce the leakage current of the device by increasing the work-function of the gate, variation of poly doping; halo doping and threshold implant concentration to reduce the leakage current of the device. To diminish these problems in Nano-scale transistors; there is massive interest in the variation of transistor's gate work-function. The experimental observations show that the devices with high gate work-function material have low leakage current as compared to low gate work-function devices. In this paper, 45nm P-MOSFET is virtually fabricated in ATHENA and simulated in ATLAS SILVACO. The workfunction of the gate of PMOS is varied from 5.05eV to 5.32eV to estimate the leakage current of the device. The simulation result shows that the 9.35 nA/µm is achieved at gate work-function of 5.25eV.
pMOSFET with 200% mobility enhancement induced by multiple stressors
IEEE Electron Device Letters, 2006
Recessed Si 0.8 Ge 0.2 source/drain (S/D) and a compressive contact etch-stop layer have been successfully integrated resulting in nearly 200% improvement in hole mobility. This is the largest reported process-induced hole mobility enhancement to the authors' knowledge. This letter demonstrates that a drivecurrent improvement from recessed Si 0.8 Ge 0.2 plus the compressive nitride layer are in fact additive. Furthermore, it shows that the mobility enhancement is a superlinear function of stress, leading to larger than additive gains in the drive current when combining several stress sources.
Microscopic analysis of the impact of substrate bias on the gate current of pMOSFETs
2001
This paper presents a detailed numerical investigation of the recently reported phenomenon of substrate enhanced hole gate current in deep submicron pMOS transistors. To this purpose, full-band Monte Carlo simulations of carrier heating and injection in the gate oxide have been carried out at different substrate voltages. Results are in good qualitative agreement with previously reported measurements, and provide a clear microscopic picture to explain the experimentally observed features of electron and hole gate currents in pMOS devices
Modeling the short-channel threshold voltage of a novel vertical heterojunction pMOSFET
IEEE Transactions on Electron Devices, 1999
Analytical modeling of the threshold voltage of a Si 10x Ge x /Si heterojunction pMOSFET has been performed using a quasi-two-dimensional (quasi-2-D) approach for the calculation of the potential. It is shown that the use of Si 10x Ge x in the source region leads to an improvement in the short-channel behavior of deep submicron pMOSFET's. The V T roll-off can be substantially decreased by introducing a material dependent barrier between source and channel. Furthermore it will be proven that this advantage will become stronger when channel lengths are decreased toward the deep submicron regime.
—High-performance PMOSFETs with sub-50–nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-aligned to each other and to the source/drain (S/D) regions; 3) raised S/D regions; and 4) a short (50 nm) Si fin to maintain quasi-planar topology for ease of fabrication. The 45-nm gate-length p-channel FinFET showed an dsat of 820 A/ m at ds = gs = 1 2 V and ox = 2 5 nm. Devices showed good performance down to a gate-length of 18 nm. Excellent short-channel behavior was observed. The fin thickness (corresponding to twice the body thickness) is found to be critical for suppressing the short-channel effects. Simulations indicate that the FinFET structure can work down to 10 nm gate length. Thus, the FinFET is a very promising structure for scaling CMOS beyond 50 nm.
Advanced PMOS Device Architecture for Highly-Doped Ultra-Shallow Junctions
Japanese Journal of Applied Physics, 2004
In this paper we study the integration of Boron ultra-shallow junctions (USJ) obtained by Germanium pre-amorphization, Fluorine co-implantation and fast ramp-up and ramp-down anneals into advanced p-channel metal-oxide-semiconductor (PMOS) devices. Several integration issues associated to these USJ are investigated: short-channel effects control, implantation tilt angle influence, junction de-activation, thermal budget, silicide process. We show that remarkable PMOS device performance enhancement (I on ¼ 450 mA/mm at I off ¼ 250 nA/mm for devices with L g ¼ $ 50 nm) can be achieved when full potential of highly-active and abrupt USJ is exploited by combining it with a low thermal budget integration scheme and a low contact resistance NiSi.