AArch64AsmBackend.cpp Source File (original) (raw)

27using namespace llvm;

29namespace {

31class AArch64AsmBackend : public MCAsmBackend {

32protected:

33 Triple TheTriple;

35public:

36 AArch64AsmBackend(const Target &T, const Triple &TT, bool IsLittleEndian)

39 TheTriple(TT) {}

42 std::optional getFixupKind(StringRef Name) const override;

44 MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override {

50 {"fixup_aarch64_pcrel_adr_imm21", 0, 32, 0},

51 {"fixup_aarch64_pcrel_adrp_imm21", 0, 32, 0},

52 {"fixup_aarch64_add_imm12", 10, 12, 0},

53 {"fixup_aarch64_ldst_imm12_scale1", 10, 12, 0},

54 {"fixup_aarch64_ldst_imm12_scale2", 10, 12, 0},

55 {"fixup_aarch64_ldst_imm12_scale4", 10, 12, 0},

56 {"fixup_aarch64_ldst_imm12_scale8", 10, 12, 0},

57 {"fixup_aarch64_ldst_imm12_scale16", 10, 12, 0},

58 {"fixup_aarch64_ldr_pcrel_imm19", 5, 19, 0},

59 {"fixup_aarch64_movw", 5, 16, 0},

60 {"fixup_aarch64_pcrel_branch9", 5, 9, 0},

61 {"fixup_aarch64_pcrel_branch14", 5, 14, 0},

62 {"fixup_aarch64_pcrel_branch16", 5, 16, 0},

63 {"fixup_aarch64_pcrel_branch19", 5, 19, 0},

64 {"fixup_aarch64_pcrel_branch26", 0, 26, 0},

65 {"fixup_aarch64_pcrel_call26", 0, 26, 0}};

70 return {};

77 "Invalid kind!");

79 }

81 void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target,

82 uint8_t *Data, uint64_t Value, bool IsResolved) override;

84 bool fixupNeedsRelaxation(const MCFixup &Fixup,

85 uint64_t Value) const override;

86 bool writeNopData(raw_ostream &OS, uint64_t Count,

87 const MCSubtargetInfo *STI) const override;

89 unsigned getFixupKindContainereSizeInBytes(unsigned Kind) const;

90};

92}

96 switch (Kind) {

97 default:

101 return 1;

102

105 return 2;

106

119 return 3;

120

127 return 4;

128

130 return 8;

131 }

132}

133

135 unsigned lo2 = Value & 0x3;

136 unsigned hi19 = (Value & 0x1ffffc) >> 2;

137 return (hi19 << 5) | (lo2 << 29);

138}

139

142 const Triple &TheTriple, bool IsResolved) {

143 int64_t SignedValue = static_cast<int64_t>(Value);

144 switch (Fixup.getKind()) {

145 default:

149 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");

155 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");

157 }

161

163 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");

165 Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned");

166

167 return (Value >> 2) & 0x7ffff;

172

174 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");

179

181 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");

183 Ctx.reportError(Fixup.getLoc(), "fixup must be 2-byte aligned");

184 return Value >> 1;

188

190 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");

192 Ctx.reportError(Fixup.getLoc(), "fixup must be 4-byte aligned");

193 return Value >> 2;

197

199 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");

201 Ctx.reportError(Fixup.getLoc(), "fixup must be 8-byte aligned");

202 return Value >> 3;

206

208 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");

210 Ctx.reportError(Fixup.getLoc(), "fixup must be 16-byte aligned");

211 return Value >> 4;

217 if (!RefKind) {

218

219 if (SignedValue > 0xFFFF || SignedValue < -0xFFFF)

220 Ctx.reportError(Fixup.getLoc(),

221 "fixup value out of range [-0xFFFF, 0xFFFF]");

222

223

224 if (SignedValue < 0)

225 SignedValue = ~SignedValue;

227 } else

228

229

230 Ctx.reportError(Fixup.getLoc(),

231 "relocation for a thread-local variable points to an "

232 "absolute symbol");

234 }

235

236 if (!IsResolved) {

237

238

239 Ctx.reportError(Fixup.getLoc(), "unresolved movw fixup not yet "

240 "implemented");

242 }

243

247 break;

249 SignedValue = SignedValue >> 16;

250 break;

252 SignedValue = SignedValue >> 32;

253 break;

255 SignedValue = SignedValue >> 48;

256 break;

257 default:

258 llvm_unreachable("Variant kind doesn't correspond to fixup");

259 }

260

261 } else {

264 break;

267 break;

270 break;

273 break;

274 default:

275 llvm_unreachable("Variant kind doesn't correspond to fixup");

276 }

277 }

278

282 if (SignedValue > 0xFFFF || SignedValue < -0xFFFF)

283 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");

284

285

286 if (SignedValue < 0)

287 SignedValue = ~SignedValue;

289 } else if (Value > 0xFFFF) {

290 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");

291 }

293 }

295

297 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");

298

299 if (Value & 0b11)

300 Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned");

301 return (Value >> 2) & 0x1ff;

303

305 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");

306

308 Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned");

309 return (Value >> 2) & 0x3fff;

311

312 SignedValue = -SignedValue;

314

315 if (SignedValue < 0 || SignedValue > ((1 << 18) - 1))

316 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");

317

318 if (Value & 0b11)

319 Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned");

320 return (Value >> 2) & 0xffff;

323 if (TheTriple.isOSBinFormatCOFF() && !IsResolved && SignedValue != 0) {

324

325

326 Ctx.reportError(Fixup.getLoc(),

327 "cannot perform a PC-relative fixup with a non-zero "

328 "symbol offset");

329 }

330

332 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");

333

335 Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned");

336 return (Value >> 2) & 0x3ffffff;

344 }

345}

346

347std::optional

348AArch64AsmBackend::getFixupKind(StringRef Name) const {

350 return std::nullopt;

351

352 unsigned Type = llvm::StringSwitch(Name)

353#define ELF_RELOC(X, Y) .Case(#X, Y)

354#include "llvm/BinaryFormat/ELFRelocs/AArch64.def"

355#undef ELF_RELOC

356 .Case("BFD_RELOC_NONE", ELF::R_AARCH64_NONE)

357 .Case("BFD_RELOC_16", ELF::R_AARCH64_ABS16)

358 .Case("BFD_RELOC_32", ELF::R_AARCH64_ABS32)

359 .Case("BFD_RELOC_64", ELF::R_AARCH64_ABS64)

360 .Default(-1u);

361 if (Type == -1u)

362 return std::nullopt;

364}

365

366

367

368unsigned AArch64AsmBackend::getFixupKindContainereSizeInBytes(unsigned Kind) const {

370 return 0;

371

372 switch (Kind) {

373 default:

375

377 return 1;

379 return 2;

381 return 4;

383 return 8;

384

401

402 return 0;

403 }

404}

405

407

408

409

410

411

412

413

414

415

416

417

418

420}

421

422void AArch64AsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup,

423 const MCValue &Target, uint8_t *Data,

424 uint64_t Value, bool IsResolved) {

426 IsResolved = false;

427 maybeAddReloc(F, Fixup, Target, Value, IsResolved);

430 return;

431

437 if (!Expr) {

439 "expected relocatable expression");

440 return;

441 }

443 Value = (uint64_t(Expr->getDiscriminator()) << 32) |

444 (uint64_t(Expr->getKey()) << 60) |

445 (uint64_t(Expr->hasAddressDiversity()) << 63);

446 }

447 }

448

450 return;

452 MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());

454 int64_t SignedValue = static_cast<int64_t>(Value);

455

457

458

460

461 assert(Fixup.getOffset() + NumBytes <= F.getSize() &&

462 "Invalid fixup offset!");

463

464

465 unsigned FulleSizeInBytes = getFixupKindContainereSizeInBytes(Fixup.getKind());

466

467

468

469 if (FulleSizeInBytes == 0) {

470

471 for (unsigned i = 0; i != NumBytes; ++i) {

472 Data[i] |= uint8_t((Value >> (i * 8)) & 0xff);

473 }

474 } else {

475

476 assert(Fixup.getOffset() + FulleSizeInBytes <= F.getSize() &&

477 "Invalid fixup size!");

478 assert(NumBytes <= FulleSizeInBytes && "Invalid fixup size!");

479 for (unsigned i = 0; i != NumBytes; ++i) {

480 unsigned Idx = FulleSizeInBytes - 1 - i;

481 Data[Idx] |= uint8_t((Value >> (i * 8)) & 0xff);

482 }

483 }

484

485

486

491

492

493 if (SignedValue < 0)

494 Data[3] &= ~(1 << 6);

495 else

496 Data[3] |= (1 << 6);

497 }

498}

499

500bool AArch64AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,

501 uint64_t Value) const {

502

503

504

505

506 return int64_t(Value) != int64_t(int8_t(Value));

507}

508

509bool AArch64AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,

510 const MCSubtargetInfo *STI) const {

511

512

513

515

516

518 for (uint64_t i = 0; i != Count; ++i)

519 OS.write("\x1f\x20\x03\xd5", 4);

520 return true;

521}

522

523namespace {

524

526

527

529

530

531 UNWIND_ARM64_MODE_FRAMELESS = 0x02000000,

532

533

534

535

536

537

538 UNWIND_ARM64_MODE_DWARF = 0x03000000,

539

540

541

542

543

544

545

546 UNWIND_ARM64_MODE_FRAME = 0x04000000,

547

548

549 UNWIND_ARM64_FRAME_X19_X20_PAIR = 0x00000001,

550 UNWIND_ARM64_FRAME_X21_X22_PAIR = 0x00000002,

551 UNWIND_ARM64_FRAME_X23_X24_PAIR = 0x00000004,

552 UNWIND_ARM64_FRAME_X25_X26_PAIR = 0x00000008,

553 UNWIND_ARM64_FRAME_X27_X28_PAIR = 0x00000010,

554 UNWIND_ARM64_FRAME_D8_D9_PAIR = 0x00000100,

555 UNWIND_ARM64_FRAME_D10_D11_PAIR = 0x00000200,

556 UNWIND_ARM64_FRAME_D12_D13_PAIR = 0x00000400,

557 UNWIND_ARM64_FRAME_D14_D15_PAIR = 0x00000800

558};

559

560}

561

562

563class DarwinAArch64AsmBackend : public AArch64AsmBackend {

565

566

567

568

570 return (StackSize / 16) << 12;

571 }

572

573public:

574 DarwinAArch64AsmBackend(const Target &T, const Triple &TT,

575 const MCRegisterInfo &MRI)

576 : AArch64AsmBackend(T, TT, true), MRI(MRI) {}

577

578 std::unique_ptr

579 createObjectTargetWriter() const override {

584 }

585

586

587 uint64_t generateCompactUnwindEncoding(const MCDwarfFrameInfo *FI,

588 const MCContext *Ctxt) const override {

589

590

592 return CU::UNWIND_ARM64_MODE_DWARF;

593

595 if (Instrs.empty())

596 return CU::UNWIND_ARM64_MODE_FRAMELESS;

597 if (!isDarwinCanonicalPersonality(FI->Personality) &&

599 return CU::UNWIND_ARM64_MODE_DWARF;

600

601 bool HasFP = false;

602 uint64_t StackSize = 0;

603

604 uint64_t CompactUnwindEncoding = 0;

605 int64_t CurOffset = 0;

606 for (size_t i = 0, e = Instrs.size(); i != e; ++i) {

607 const MCCFIInstruction &Inst = Instrs[i];

608

610 default:

611

612 return CU::UNWIND_ARM64_MODE_DWARF;

614

615 MCRegister XReg =

617

618

619

620

621

622 if (XReg != AArch64::FP)

623 return CU::UNWIND_ARM64_MODE_DWARF;

624

625 if (i + 2 >= e)

626 return CU::UNWIND_ARM64_MODE_DWARF;

627

628 const MCCFIInstruction &LRPush = Instrs[++i];

630 return CU::UNWIND_ARM64_MODE_DWARF;

631 const MCCFIInstruction &FPPush = Instrs[++i];

633 return CU::UNWIND_ARM64_MODE_DWARF;

634

636 return CU::UNWIND_ARM64_MODE_DWARF;

638

639 MCRegister LRReg = *MRI.getLLVMRegNum(LRPush.getRegister(), true);

641

644

645 if (LRReg != AArch64::LR || FPReg != AArch64::FP)

646 return CU::UNWIND_ARM64_MODE_DWARF;

647

648

649 CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAME;

651 break;

652 }

654 if (StackSize != 0)

655 return CU::UNWIND_ARM64_MODE_DWARF;

656 StackSize = std::abs(Inst.getOffset());

657 break;

658 }

660

661

662 MCRegister Reg1 = *MRI.getLLVMRegNum(Inst.getRegister(), true);

663 if (i + 1 == e)

664 return CU::UNWIND_ARM64_MODE_DWARF;

665

666 if (CurOffset != 0 && Inst.getOffset() != CurOffset - 8)

667 return CU::UNWIND_ARM64_MODE_DWARF;

669

670 const MCCFIInstruction &Inst2 = Instrs[++i];

672 return CU::UNWIND_ARM64_MODE_DWARF;

673 MCRegister Reg2 = *MRI.getLLVMRegNum(Inst2.getRegister(), true);

674

675 if (Inst2.getOffset() != CurOffset - 8)

676 return CU::UNWIND_ARM64_MODE_DWARF;

678

679

680

681

682

683

684

685

686

689

690 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 &&

691 (CompactUnwindEncoding & 0xF1E) == 0)

692 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X19_X20_PAIR;

693 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 &&

694 (CompactUnwindEncoding & 0xF1C) == 0)

695 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X21_X22_PAIR;

696 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 &&

697 (CompactUnwindEncoding & 0xF18) == 0)

698 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X23_X24_PAIR;

699 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 &&

700 (CompactUnwindEncoding & 0xF10) == 0)

701 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X25_X26_PAIR;

702 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 &&

703 (CompactUnwindEncoding & 0xF00) == 0)

704 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X27_X28_PAIR;

705 else {

708

709

710

711

712

713 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 &&

714 (CompactUnwindEncoding & 0xE00) == 0)

715 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D8_D9_PAIR;

716 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 &&

717 (CompactUnwindEncoding & 0xC00) == 0)

718 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D10_D11_PAIR;

719 else if (Reg1 == AArch64::D12 && Reg2 == AArch64::D13 &&

720 (CompactUnwindEncoding & 0x800) == 0)

721 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D12_D13_PAIR;

722 else if (Reg1 == AArch64::D14 && Reg2 == AArch64::D15)

723 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D14_D15_PAIR;

724 else

725

726 return CU::UNWIND_ARM64_MODE_DWARF;

727 }

728

729 break;

730 }

731 }

732 }

733

734 if (!HasFP) {

735

736

737 if (StackSize > 65520)

738 return CU::UNWIND_ARM64_MODE_DWARF;

739

740 CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAMELESS;

741 CompactUnwindEncoding |= encodeStackAdjustment(StackSize);

742 }

743

744 return CompactUnwindEncoding;

745 }

746};

747

748}

749

750namespace {

751

752class ELFAArch64AsmBackend : public AArch64AsmBackend {

753public:

754 uint8_t OSABI;

755 bool IsILP32;

756

757 ELFAArch64AsmBackend(const Target &T, const Triple &TT, uint8_t OSABI,

758 bool IsLittleEndian, bool IsILP32)

759 : AArch64AsmBackend(T, TT, IsLittleEndian), OSABI(OSABI),

760 IsILP32(IsILP32) {}

761

762 std::unique_ptr

763 createObjectTargetWriter() const override {

765 }

766};

767

768}

769

770namespace {

771class COFFAArch64AsmBackend : public AArch64AsmBackend {

772public:

773 COFFAArch64AsmBackend(const Target &T, const Triple &TheTriple)

774 : AArch64AsmBackend(T, TheTriple, true) {}

775

776 std::unique_ptr

777 createObjectTargetWriter() const override {

779 }

780};

781}

782

789 return new DarwinAArch64AsmBackend(T, TheTriple, MRI);

790 }

791

793 return new COFFAArch64AsmBackend(T, TheTriple);

794

796

799 return new ELFAArch64AsmBackend(T, TheTriple, OSABI, true,

800 IsILP32);

801}

802

809 "Big endian is only supported for ELF targets!");

812 return new ELFAArch64AsmBackend(T, TheTriple, OSABI, false,

813 IsILP32);

814}

unsigned const MachineRegisterInfo * MRI

static unsigned AdrImmBits(unsigned Value)

Definition AArch64AsmBackend.cpp:134

static unsigned getFixupKindNumBytes(unsigned Kind)

The number of bytes the fixup may change.

Definition AArch64AsmBackend.cpp:95

static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target, uint64_t Value, MCContext &Ctx, const Triple &TheTriple, bool IsResolved)

Definition AArch64AsmBackend.cpp:140

static bool shouldForceRelocation(const MCFixup &Fixup)

Definition AArch64AsmBackend.cpp:406

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

Analysis containing CSE Info

PowerPC TLS Dynamic Call Fixup

static constexpr MCPhysReg FPReg

size_t size() const

size - Get the array size.

bool empty() const

empty - Check if the array is empty.

Generic interface to target specific assembler backends.

virtual MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const

Get information on a fixup kind.

unsigned getRegister() const

OpType getOperation() const

int64_t getOffset() const

Context object for machine code objects.

LLVM_ABI bool emitCompactUnwindNonCanonical() const

Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...

MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...

Generic base class for all target subtargets.

const Triple & getTargetTriple() const

StringRef - Represent a constant reference to a string, i.e.

Target - Wrapper for Target specific information.

Triple - Helper class for working with autoconf configuration names.

bool isOSBinFormatMachO() const

Tests whether the environment is MachO.

OSType getOS() const

Get the parsed operating system type of this triple.

bool isOSBinFormatCOFF() const

Tests whether the OS uses the COFF binary format.

EnvironmentType getEnvironment() const

Get the parsed environment type of this triple.

LLVM_ABI bool isArch32Bit() const

Test whether the architecture is 32-bit.

bool isOSBinFormatELF() const

Tests whether the OS uses the ELF binary format.

LLVM Value Representation.

raw_ostream & write_zeros(unsigned NumZeros)

write_zeros - Insert 'NumZeros' nulls.

raw_ostream & write(unsigned char C)

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

CompactUnwindEncodings

Compact unwind encoding values.

Specifier getSymbolLoc(Specifier S)

@ fixup_aarch64_pcrel_branch9

@ fixup_aarch64_pcrel_branch16

@ fixup_aarch64_ldst_imm12_scale4

@ fixup_aarch64_pcrel_call26

@ fixup_aarch64_pcrel_branch26

@ fixup_aarch64_pcrel_branch19

@ fixup_aarch64_ldr_pcrel_imm19

@ fixup_aarch64_pcrel_adr_imm21

@ fixup_aarch64_pcrel_branch14

@ fixup_aarch64_ldst_imm12_scale2

@ fixup_aarch64_ldst_imm12_scale16

@ fixup_aarch64_pcrel_adrp_imm21

@ fixup_aarch64_add_imm12

@ fixup_aarch64_ldst_imm12_scale8

@ fixup_aarch64_ldst_imm12_scale1

Specifier getAddressFrag(Specifier S)

LLVM_ABI Expected< uint32_t > getCPUSubType(const Triple &T)

LLVM_ABI Expected< uint32_t > getCPUType(const Triple &T)

VE::Fixups getFixupKind(uint8_t S)

Error applyFixup(LinkGraph &G, Block &B, const Edge &E, const ArmConfig &ArmCfg)

Apply fixup expression for edge to block content.

bool isRelocation(MCFixupKind FixupKind)

Context & getContext() const

This is an optimization pass for GlobalISel generic memory operations.

FunctionAddr VTableAddr Value

constexpr bool isInt(int64_t x)

Checks if an integer fits into the given bit width.

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

std::unique_ptr< MCObjectTargetWriter > createAArch64WinCOFFObjectWriter(const Triple &TheTriple)

uint16_t MCFixupKind

Extensible enumeration to represent the type of a fixup.

MCAsmBackend * createAArch64leAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)

Definition AArch64AsmBackend.cpp:783

FunctionAddr VTableAddr Count

constexpr bool isUInt(uint64_t x)

Checks if an unsigned integer fits into the given bit width.

@ FK_SecRel_2

A two-byte section relative fixup.

@ FirstLiteralRelocationKind

@ FK_Data_8

A eight-byte fixup.

@ FK_Data_1

A one-byte fixup.

@ FK_Data_4

A four-byte fixup.

@ FK_SecRel_4

A four-byte section relative fixup.

@ FK_Data_2

A two-byte fixup.

void cantFail(Error Err, const char *Msg=nullptr)

Report a fatal error if Err is a failure value.

FunctionAddr VTableAddr uintptr_t uintptr_t Data

static MCRegister getXRegFromWReg(MCRegister Reg)

ArrayRef(const T &OneElt) -> ArrayRef< T >

std::unique_ptr< MCObjectTargetWriter > createAArch64MachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype, bool IsILP32)

MCAsmBackend * createAArch64beAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)

Definition AArch64AsmBackend.cpp:803

static MCRegister getDRegFromBReg(MCRegister Reg)

std::unique_ptr< MCObjectTargetWriter > createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32)

const MCSymbol * Personality

std::vector< MCCFIInstruction > Instructions