AArch64RegisterBankInfo.cpp Source File (original) (raw)

33#include "llvm/IR/IntrinsicsAArch64.h"

36#include

38#define GET_TARGET_REGBANK_IMPL

39#include "AArch64GenRegisterBank.inc"

42#include "AArch64GenRegisterBankInfo.def"

44using namespace llvm;

51 static auto InitializeRegisterBankOnce = [&]() {

59 (void)RBGPR;

60 assert(&AArch64::GPRRegBank == &RBGPR &&

61 "The order in RegBanks is messed up");

64 (void)RBFPR;

65 assert(&AArch64::FPRRegBank == &RBFPR &&

66 "The order in RegBanks is messed up");

69 (void)RBCCR;

70 assert(&AArch64::CCRegBank == &RBCCR &&

71 "The order in RegBanks is messed up");

75 assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&

76 "Subclass not added?");

78 "GPRs should hold up to 128-bit");

82 assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) &&

83 "Subclass not added?");

84 assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) &&

85 "Subclass not added?");

87 "FPRs should hold up to 512-bit via QQQQ sequence");

89 assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) &&

90 "Class not added?");

92 "CCR should hold up to 32-bit");

98 "PartialMappingIdx's are incorrectly ordered");

102 "PartialMappingIdx's are incorrectly ordered");

103

104

105#define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB) \

106 do { \

107 assert( \

108 checkPartialMap(PartialMappingIdx::Idx, ValStartIdx, ValLength, RB) && \

109 #Idx " is incorrectly initialized"); \

110 } while (false)

111

121

122

123#define CHECK_VALUEMAP_IMPL(RBName, Size, Offset) \

124 do { \

125 assert(checkValueMapImpl(PartialMappingIdx::PMI_##RBName##Size, \

126 PartialMappingIdx::PMI_First##RBName, Size, \

127 Offset) && \

128 #RBName #Size " " #Offset " is incorrectly initialized"); \

129 } while (false)

130

131#define CHECK_VALUEMAP(RBName, Size) CHECK_VALUEMAP_IMPL(RBName, Size, 0)

132

142

143

144

145#define CHECK_VALUEMAP_3OPS(RBName, Size) \

146 do { \

147 CHECK_VALUEMAP_IMPL(RBName, Size, 0); \

148 CHECK_VALUEMAP_IMPL(RBName, Size, 1); \

149 CHECK_VALUEMAP_IMPL(RBName, Size, 2); \

150 } while (false)

151

160

161#define CHECK_VALUEMAP_CROSSREGCPY(RBNameDst, RBNameSrc, Size) \

162 do { \

163 unsigned PartialMapDstIdx = PMI_##RBNameDst##Size - PMI_Min; \

164 unsigned PartialMapSrcIdx = PMI_##RBNameSrc##Size - PMI_Min; \

165 (void)PartialMapDstIdx; \

166 (void)PartialMapSrcIdx; \

167 const ValueMapping *Map = getCopyMapping(AArch64::RBNameDst##RegBankID, \

168 AArch64::RBNameSrc##RegBankID, \

169 TypeSize::getFixed(Size)); \

170 (void)Map; \

171 assert(Map[0].BreakDown == \

172 &AArch64GenRegisterBankInfo::PartMappings[PartialMapDstIdx] && \

173 Map[0].NumBreakDowns == 1 && \

174 #RBNameDst #Size " Dst is incorrectly initialized"); \

175 assert(Map[1].BreakDown == \

176 &AArch64GenRegisterBankInfo::PartMappings[PartialMapSrcIdx] && \

177 Map[1].NumBreakDowns == 1 && \

178 #RBNameSrc #Size " Src is incorrectly initialized"); \

179 \

180 } while (false)

181

190

191#define CHECK_VALUEMAP_FPEXT(DstSize, SrcSize) \

192 do { \

193 unsigned PartialMapDstIdx = PMI_FPR##DstSize - PMI_Min; \

194 unsigned PartialMapSrcIdx = PMI_FPR##SrcSize - PMI_Min; \

195 (void)PartialMapDstIdx; \

196 (void)PartialMapSrcIdx; \

197 const ValueMapping *Map = getFPExtMapping(DstSize, SrcSize); \

198 (void)Map; \

199 assert(Map[0].BreakDown == \

200 &AArch64GenRegisterBankInfo::PartMappings[PartialMapDstIdx] && \

201 Map[0].NumBreakDowns == 1 && "FPR" #DstSize \

202 " Dst is incorrectly initialized"); \

203 assert(Map[1].BreakDown == \

204 &AArch64GenRegisterBankInfo::PartMappings[PartialMapSrcIdx] && \

205 Map[1].NumBreakDowns == 1 && "FPR" #SrcSize \

206 " Src is incorrectly initialized"); \

207 \

208 } while (false)

209

214

215 assert(verify(TRI) && "Invalid register bank information");

216 };

217

218 llvm::call_once(InitializeRegisterBankFlag, InitializeRegisterBankOnce);

219}

220

224

225

226

227

228

229

230

231

232 if (&A == &AArch64::GPRRegBank && &B == &AArch64::FPRRegBank)

233

234 return 5;

235 if (&A == &AArch64::FPRRegBank && &B == &AArch64::GPRRegBank)

236

237 return 4;

238

240}

241

244 LLT Ty) const {

245 switch (RC.getID()) {

246 case AArch64::GPR64sponlyRegClassID:

247 return getRegBank(AArch64::GPRRegBankID);

248 default:

250 }

251}

252

260

261 switch (MI.getOpcode()) {

262 case TargetOpcode::G_OR: {

263

264

266 if (Size != 32 && Size != 64)

267 break;

268

269

270

271 if (MI.getNumOperands() != 3)

272 break;

276 3);

279 3);

280

281 AltMappings.push_back(&GPRMapping);

282 AltMappings.push_back(&FPRMapping);

283 return AltMappings;

284 }

285 case TargetOpcode::G_BITCAST: {

287 if (Size != 32 && Size != 64)

288 break;

289

290

291

292 if (MI.getNumOperands() != 2)

293 break;

294

297 1, 1,

299 2);

301 2, 1,

303 2);

305 3,

306

307 copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank,

310 2);

312 3,

313

314 copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank,

317 2);

318

319 AltMappings.push_back(&GPRMapping);

320 AltMappings.push_back(&FPRMapping);

321 AltMappings.push_back(&GPRToFPRMapping);

322 AltMappings.push_back(&FPRToGPRMapping);

323 return AltMappings;

324 }

325 case TargetOpcode::G_LOAD: {

327 if (Size != 64)

328 break;

329

330

331

332 if (MI.getNumOperands() != 2)

333 break;

334

337 1, 1,

340

342 2);

344 2, 1,

347

349 2);

350

351 AltMappings.push_back(&GPRMapping);

352 AltMappings.push_back(&FPRMapping);

353 return AltMappings;

354 }

355 default:

356 break;

357 }

359}

360

361void AArch64RegisterBankInfo::applyMappingImpl(

362 MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const {

365

366 switch (MI.getOpcode()) {

367 case TargetOpcode::G_OR:

368 case TargetOpcode::G_BITCAST:

369 case TargetOpcode::G_LOAD:

370

371 assert((OpdMapper.getInstrMapping().getID() >= 1 &&

372 OpdMapper.getInstrMapping().getID() <= 4) &&

373 "Don't know how to handle that ID");

375 case TargetOpcode::G_INSERT_VECTOR_ELT: {

376

377 Builder.setInsertPt(*MI.getParent(), MI.getIterator());

378 auto Ext = Builder.buildAnyExt(LLT::scalar(32), MI.getOperand(2).getReg());

379 MRI.setRegBank(Ext.getReg(0), getRegBank(AArch64::GPRRegBankID));

380 MI.getOperand(2).setReg(Ext.getReg(0));

382 }

383 case AArch64::G_DUP: {

384

385 assert(MRI.getType(MI.getOperand(1).getReg()).getSizeInBits() < 32 &&

386 "Expected sources smaller than 32-bits");

387 Builder.setInsertPt(*MI.getParent(), MI.getIterator());

388

390 auto ConstMI = MRI.getVRegDef(MI.getOperand(1).getReg());

391 if (ConstMI->getOpcode() == TargetOpcode::G_CONSTANT) {

392 auto CstVal = ConstMI->getOperand(1).getCImm()->getValue();

393 ConstReg =

394 Builder.buildConstant(LLT::scalar(32), CstVal.sext(32)).getReg(0);

395 } else {

398 }

399 MRI.setRegBank(ConstReg, getRegBank(AArch64::GPRRegBankID));

400 MI.getOperand(1).setReg(ConstReg);

402 }

403 default:

405 }

406}

407

409AArch64RegisterBankInfo::getSameKindOfOperandsMapping(

411 const unsigned Opc = MI.getOpcode();

412 const MachineFunction &MF = *MI.getParent()->getParent();

413 const MachineRegisterInfo &MRI = MF.getRegInfo();

414

415 unsigned NumOperands = MI.getNumOperands();

416 assert(NumOperands <= 3 &&

417 "This code is for instructions with 3 or less operands");

418

419 LLT Ty = MRI.getType(MI.getOperand(0).getReg());

422

424

425#ifndef NDEBUG

426

427

428

429

430

431

432

433

434 for (unsigned Idx = 1; Idx != NumOperands; ++Idx) {

435 LLT OpTy = MRI.getType(MI.getOperand(Idx).getReg());

440 "Operand has incompatible size");

442 (void)OpIsFPR;

443 assert(IsFPR == OpIsFPR && "Operand has incompatible type");

444 }

445#endif

446

449}

450

451

454

456 default:

457 return false;

458 case Intrinsic::aarch64_neon_uaddlv:

459 case Intrinsic::aarch64_neon_uaddv:

460 case Intrinsic::aarch64_neon_saddv:

461 case Intrinsic::aarch64_neon_umaxv:

462 case Intrinsic::aarch64_neon_smaxv:

463 case Intrinsic::aarch64_neon_uminv:

464 case Intrinsic::aarch64_neon_sminv:

465 case Intrinsic::aarch64_neon_faddv:

466 case Intrinsic::aarch64_neon_fmaxv:

467 case Intrinsic::aarch64_neon_fminv:

468 case Intrinsic::aarch64_neon_fmaxnmv:

469 case Intrinsic::aarch64_neon_fminnmv:

470 case Intrinsic::aarch64_neon_fmulx:

471 case Intrinsic::aarch64_neon_frecpe:

472 case Intrinsic::aarch64_neon_frecps:

473 case Intrinsic::aarch64_neon_frecpx:

474 case Intrinsic::aarch64_neon_frsqrte:

475 case Intrinsic::aarch64_neon_frsqrts:

476 case Intrinsic::aarch64_neon_facge:

477 case Intrinsic::aarch64_neon_facgt:

478 case Intrinsic::aarch64_neon_fabd:

479 case Intrinsic::aarch64_sisd_fabd:

480 case Intrinsic::aarch64_neon_sqrdmlah:

481 case Intrinsic::aarch64_neon_sqrdmlsh:

482 case Intrinsic::aarch64_neon_sqrdmulh:

483 case Intrinsic::aarch64_neon_sqadd:

484 case Intrinsic::aarch64_neon_sqsub:

485 case Intrinsic::aarch64_crypto_sha1h:

486 case Intrinsic::aarch64_crypto_sha1c:

487 case Intrinsic::aarch64_crypto_sha1p:

488 case Intrinsic::aarch64_crypto_sha1m:

489 case Intrinsic::aarch64_sisd_fcvtxn:

490 return true;

491 case Intrinsic::aarch64_neon_saddlv: {

492 const LLT SrcTy = MRI.getType(MI.getOperand(2).getReg());

493 return SrcTy.getElementType().getSizeInBits() >= 16 &&

494 SrcTy.getElementCount().getFixedValue() >= 4;

495 }

496 }

497}

498

499bool AArch64RegisterBankInfo::isPHIWithFPConstraints(

502 if (.isPHI() || Depth > MaxFPRSearchDepth)

503 return false;

504

505 return any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),

506 [&](const MachineInstr &UseMI) {

507 if (onlyUsesFP(UseMI, MRI, TRI, Depth + 1))

508 return true;

509 return isPHIWithFPConstraints(UseMI, MRI, TRI, Depth + 1);

510 });

511}

512

513bool AArch64RegisterBankInfo::hasFPConstraints(const MachineInstr &MI,

516 unsigned Depth) const {

517 unsigned Op = MI.getOpcode();

519 return true;

520

521

523 return true;

524

525

526

527 if (Op != TargetOpcode::COPY && .isPHI() &&

529 return false;

530

531

533 if (RB == &AArch64::FPRRegBank)

534 return true;

535 if (RB == &AArch64::GPRRegBank)

536 return false;

537

538

539

540

541

542 if (.isPHI() || Depth > MaxFPRSearchDepth)

543 return false;

544

545 return any_of(MI.explicit_uses(), [&](const MachineOperand &Op) {

546 return Op.isReg() &&

547 onlyDefinesFP(*MRI.getVRegDef(Op.getReg()), MRI, TRI, Depth + 1);

548 });

549}

550

551bool AArch64RegisterBankInfo::onlyUsesFP(const MachineInstr &MI,

554 unsigned Depth) const {

555 switch (MI.getOpcode()) {

556 case TargetOpcode::G_FPTOSI:

557 case TargetOpcode::G_FPTOUI:

558 case TargetOpcode::G_FPTOSI_SAT:

559 case TargetOpcode::G_FPTOUI_SAT:

560 case TargetOpcode::G_FCMP:

561 case TargetOpcode::G_LROUND:

562 case TargetOpcode::G_LLROUND:

563 case AArch64::G_PMULL:

564 return true;

565 case TargetOpcode::G_INTRINSIC:

567 case Intrinsic::aarch64_neon_fcvtas:

568 case Intrinsic::aarch64_neon_fcvtau:

569 case Intrinsic::aarch64_neon_fcvtzs:

570 case Intrinsic::aarch64_neon_fcvtzu:

571 case Intrinsic::aarch64_neon_fcvtms:

572 case Intrinsic::aarch64_neon_fcvtmu:

573 case Intrinsic::aarch64_neon_fcvtns:

574 case Intrinsic::aarch64_neon_fcvtnu:

575 case Intrinsic::aarch64_neon_fcvtps:

576 case Intrinsic::aarch64_neon_fcvtpu:

577 return true;

578 default:

579 break;

580 }

581 break;

582 default:

583 break;

584 }

586}

587

588bool AArch64RegisterBankInfo::onlyDefinesFP(const MachineInstr &MI,

591 unsigned Depth) const {

592 switch (MI.getOpcode()) {

593 case AArch64::G_DUP:

594 case AArch64::G_SADDLP:

595 case AArch64::G_UADDLP:

596 case TargetOpcode::G_SITOFP:

597 case TargetOpcode::G_UITOFP:

598 case TargetOpcode::G_EXTRACT_VECTOR_ELT:

599 case TargetOpcode::G_INSERT_VECTOR_ELT:

600 case TargetOpcode::G_BUILD_VECTOR:

601 case TargetOpcode::G_BUILD_VECTOR_TRUNC:

602 return true;

603 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:

605 case Intrinsic::aarch64_neon_ld1x2:

606 case Intrinsic::aarch64_neon_ld1x3:

607 case Intrinsic::aarch64_neon_ld1x4:

608 case Intrinsic::aarch64_neon_ld2:

609 case Intrinsic::aarch64_neon_ld2lane:

610 case Intrinsic::aarch64_neon_ld2r:

611 case Intrinsic::aarch64_neon_ld3:

612 case Intrinsic::aarch64_neon_ld3lane:

613 case Intrinsic::aarch64_neon_ld3r:

614 case Intrinsic::aarch64_neon_ld4:

615 case Intrinsic::aarch64_neon_ld4lane:

616 case Intrinsic::aarch64_neon_ld4r:

617 return true;

618 default:

619 break;

620 }

621 break;

622 default:

623 break;

624 }

626}

627

628bool AArch64RegisterBankInfo::prefersFPUse(const MachineInstr &MI,

631 unsigned Depth) const {

632 switch (MI.getOpcode()) {

633 case TargetOpcode::G_SITOFP:

634 case TargetOpcode::G_UITOFP:

635 return MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() ==

636 MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();

637 }

639}

640

641bool AArch64RegisterBankInfo::isLoadFromFPType(const MachineInstr &MI) const {

642

644 const Value *LdVal = MemOp->getMMO().getValue();

645 if (!LdVal)

646 return false;

647

648 Type *EltTy = nullptr;

650 EltTy = GV->getValueType();

651

652

654 if (StructEltTy->getNumElements() == 0)

655 break;

656 EltTy = StructEltTy->getTypeAtIndex(0U);

657 }

658

662

663

664 for (const auto *LdUser : LdVal->users()) {

666 EltTy = LdUser->getType();

667 break;

668 }

669 if (isa(LdUser) && LdUser->getOperand(1) == LdVal) {

670 EltTy = LdUser->getOperand(0)->getType();

671 break;

672 }

673 }

674 }

676}

677

680 const unsigned Opc = MI.getOpcode();

681

682

683

685 Opc == TargetOpcode::G_PHI) {

689 return Mapping;

690 }

691

696

697 switch (Opc) {

698

699

700 case TargetOpcode::G_ADD:

701 case TargetOpcode::G_SUB:

702 case TargetOpcode::G_PTR_ADD:

703 case TargetOpcode::G_MUL:

704 case TargetOpcode::G_SDIV:

705 case TargetOpcode::G_UDIV:

706

707 case TargetOpcode::G_AND:

708 case TargetOpcode::G_OR:

709 case TargetOpcode::G_XOR:

710

711 case TargetOpcode::G_FADD:

712 case TargetOpcode::G_FSUB:

713 case TargetOpcode::G_FMUL:

714 case TargetOpcode::G_FDIV:

715 case TargetOpcode::G_FMAXIMUM:

716 case TargetOpcode::G_FMINIMUM:

717 return getSameKindOfOperandsMapping(MI);

718 case TargetOpcode::G_FPEXT: {

719 LLT DstTy = MRI.getType(MI.getOperand(0).getReg());

720 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());

724 2);

725 }

726

727 case TargetOpcode::G_SHL:

728 case TargetOpcode::G_LSHR:

729 case TargetOpcode::G_ASHR: {

730 LLT ShiftAmtTy = MRI.getType(MI.getOperand(2).getReg());

731 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());

732 if (ShiftAmtTy.getSizeInBits() == 64 && SrcTy.getSizeInBits() == 32)

735 return getSameKindOfOperandsMapping(MI);

736 }

737 case TargetOpcode::COPY: {

738 Register DstReg = MI.getOperand(0).getReg();

739 Register SrcReg = MI.getOperand(1).getReg();

740

741 if ((DstReg.isPhysical() || MRI .getType(DstReg).isValid()) ||

742 (SrcReg.isPhysical() || MRI .getType(SrcReg).isValid())) {

745 if (!DstRB)

746 DstRB = SrcRB;

747 else if (!SrcRB)

748 SrcRB = DstRB;

749

750

751 assert(DstRB && SrcRB && "Both RegBank were nullptr");

756

757 1);

758 }

759

760 [[fallthrough]];

761 }

762 case TargetOpcode::G_BITCAST: {

763 LLT DstTy = MRI.getType(MI.getOperand(0).getReg());

764 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());

767 bool SrcIsGPR = !SrcTy.isVector() && SrcTy.getSizeInBits() <= 64;

769 DstIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;

771 SrcIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;

775

776 Opc == TargetOpcode::G_BITCAST ? 2 : 1);

777 }

778 default:

779 break;

780 }

781

782 unsigned NumOperands = MI.getNumOperands();

784

785

788 for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {

789 auto &MO = MI.getOperand(Idx);

790 if (!MO.isReg() || !MO.getReg())

791 continue;

792

793 LLT Ty = MRI.getType(MO.getReg());

794 if (!Ty.isValid())

795 continue;

796 OpSize[Idx] = Ty.getSizeInBits().getKnownMinValue();

797

798

799

800

801 if (Ty.isVector())

804 (MO.isDef() && onlyDefinesFP(MI, MRI, TRI)) ||

805 (MO.isUse() && onlyUsesFP(MI, MRI, TRI)) ||

806 Ty.getSizeInBits() > 64)

808 else

810 }

811

812 unsigned Cost = 1;

813

814

815 switch (Opc) {

816 case AArch64::G_DUP: {

817 Register ScalarReg = MI.getOperand(1).getReg();

818 LLT ScalarTy = MRI.getType(ScalarReg);

819 auto ScalarDef = MRI.getVRegDef(ScalarReg);

820

821 if (ScalarDef->getOpcode() == TargetOpcode::G_LOAD)

823

826 onlyDefinesFP(*ScalarDef, MRI, TRI)))

828 else {

831

833 }

835 }

836 break;

837 }

838 case TargetOpcode::G_TRUNC: {

839 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());

840 if (!SrcTy.isVector() && SrcTy.getSizeInBits() == 128)

842 break;

843 }

844 case TargetOpcode::G_SITOFP:

845 case TargetOpcode::G_UITOFP: {

846 if (MRI.getType(MI.getOperand(0).getReg()).isVector())

847 break;

848

849

850 Register SrcReg = MI.getOperand(1).getReg();

852 MRI.getType(SrcReg).getSizeInBits() ==

853 MRI.getType(MI.getOperand(0).getReg()).getSizeInBits())

855 else

857 break;

858 }

859 case TargetOpcode::G_FPTOSI_SAT:

860 case TargetOpcode::G_FPTOUI_SAT:

861 case TargetOpcode::G_FPTOSI:

862 case TargetOpcode::G_FPTOUI: {

863 LLT DstType = MRI.getType(MI.getOperand(0).getReg());

864 if (DstType.isVector())

865 break;

868 break;

869 }

872 if (((DstSize == SrcSize) || STI.hasFeature(AArch64::FeatureFPRCVT)) &&

873 all_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),

875 return onlyUsesFP(UseMI, MRI, TRI) ||

876 prefersFPUse(UseMI, MRI, TRI);

877 }))

879 else

881 break;

882 }

883 case TargetOpcode::G_INTRINSIC_LRINT:

884 case TargetOpcode::G_INTRINSIC_LLRINT:

885 if (MRI.getType(MI.getOperand(0).getReg()).isVector())

886 break;

888 break;

889 case TargetOpcode::G_FCMP: {

890

894 OpRegBankIdx = {Idx0,

896 break;

897 }

898 case TargetOpcode::G_BITCAST:

899

900 if (OpRegBankIdx[0] != OpRegBankIdx[1])

905 break;

906 case TargetOpcode::G_LOAD: {

907

908

909

910

911

912

915 break;

916 }

917

919

921 break;

922 }

923

924

925 if (isLoadFromFPType(MI)) {

927 break;

928 }

929

930

931

932

933 if (any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),

935

936

937

938

939

940

941

942

943

944 if (isPHIWithFPConstraints(UseMI, MRI, TRI))

945 return true;

946

947 return onlyUsesFP(UseMI, MRI, TRI) ||

948 prefersFPUse(UseMI, MRI, TRI);

949 }))

951 break;

952 }

953 case TargetOpcode::G_STORE:

954

956 Register VReg = MI.getOperand(0).getReg();

957 if (!VReg)

958 break;

962 break;

963 }

964 break;

965 case TargetOpcode::G_INDEXED_STORE:

967 Register VReg = MI.getOperand(1).getReg();

968 if (!VReg)

969 break;

973 break;

974 }

975 break;

976 case TargetOpcode::G_INDEXED_SEXTLOAD:

977 case TargetOpcode::G_INDEXED_ZEXTLOAD:

978

980 break;

981 case TargetOpcode::G_INDEXED_LOAD: {

982 if (isLoadFromFPType(MI))

984 break;

985 }

986 case TargetOpcode::G_SELECT: {

987

989 break;

990

991

992

993 LLT SrcTy = MRI.getType(MI.getOperand(2).getReg());

994 if (SrcTy.isVector()) {

996 break;

997 }

998

999

1000

1001

1002 unsigned NumFP = 0;

1003

1004

1005

1006

1007

1008

1009

1010 if (any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),

1011 [&](MachineInstr &MI) { return onlyUsesFP(MI, MRI, TRI); }))

1012 ++NumFP;

1013

1014

1015

1016

1017

1018

1019

1020

1021

1022

1023

1024

1025

1026

1027 for (unsigned Idx = 2; Idx < 4; ++Idx) {

1028 Register VReg = MI.getOperand(Idx).getReg();

1032 ++NumFP;

1033 }

1034

1035

1036

1037 if (NumFP >= 2)

1039

1040 break;

1041 }

1042 case TargetOpcode::G_UNMERGE_VALUES: {

1043

1044

1046 break;

1047

1048 LLT SrcTy = MRI.getType(MI.getOperand(MI.getNumOperands()-1).getReg());

1049

1050

1051 if (SrcTy.isVector() || SrcTy == LLT::scalar(128) ||

1052 any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),

1053 [&](MachineInstr &MI) { return onlyUsesFP(MI, MRI, TRI); })) {

1054

1055 for (unsigned Idx = 0, NumOperands = MI.getNumOperands();

1056 Idx < NumOperands; ++Idx)

1058 }

1059 break;

1060 }

1061 case TargetOpcode::G_EXTRACT_VECTOR_ELT:

1062

1065

1066

1068 break;

1069 case TargetOpcode::G_INSERT_VECTOR_ELT:

1072

1073

1074 if (getRegBank(MI.getOperand(2).getReg(), MRI, TRI) == &AArch64::FPRRegBank)

1076 else {

1077

1078

1079 LLT Ty = MRI.getType(MI.getOperand(2).getReg());

1080 if (Ty.getSizeInBits() == 8 || Ty.getSizeInBits() == 16) {

1081

1083 }

1085 }

1086

1087

1089 break;

1090 case TargetOpcode::G_EXTRACT: {

1091

1092 auto Src = MI.getOperand(1).getReg();

1093 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());

1094 if (SrcTy.getSizeInBits() != 128)

1095 break;

1096 auto Idx = MRI.getRegClassOrNull(Src) == &AArch64::XSeqPairsClassRegClass

1099 OpRegBankIdx[0] = Idx;

1100 OpRegBankIdx[1] = Idx;

1101 break;

1102 }

1103 case TargetOpcode::G_BUILD_VECTOR: {

1104

1105

1107 break;

1108 Register VReg = MI.getOperand(1).getReg();

1109 if (!VReg)

1110 break;

1111

1112

1113

1114

1115

1116

1118 unsigned DefOpc = DefMI->getOpcode();

1119 const LLT SrcTy = MRI.getType(VReg);

1121 return Op.isDef() || MRI.getVRegDef(Op.getReg())->getOpcode() ==

1122 TargetOpcode::G_CONSTANT;

1123 }))

1124 break;

1126 SrcTy.getSizeInBits() < 32 ||

1128

1129

1130 unsigned NumOperands = MI.getNumOperands();

1131 for (unsigned Idx = 0; Idx < NumOperands; ++Idx)

1133 }

1134 break;

1135 }

1136 case TargetOpcode::G_VECREDUCE_FADD:

1137 case TargetOpcode::G_VECREDUCE_FMUL:

1138 case TargetOpcode::G_VECREDUCE_FMAX:

1139 case TargetOpcode::G_VECREDUCE_FMIN:

1140 case TargetOpcode::G_VECREDUCE_FMAXIMUM:

1141 case TargetOpcode::G_VECREDUCE_FMINIMUM:

1142 case TargetOpcode::G_VECREDUCE_ADD:

1143 case TargetOpcode::G_VECREDUCE_MUL:

1144 case TargetOpcode::G_VECREDUCE_AND:

1145 case TargetOpcode::G_VECREDUCE_OR:

1146 case TargetOpcode::G_VECREDUCE_XOR:

1147 case TargetOpcode::G_VECREDUCE_SMAX:

1148 case TargetOpcode::G_VECREDUCE_SMIN:

1149 case TargetOpcode::G_VECREDUCE_UMAX:

1150 case TargetOpcode::G_VECREDUCE_UMIN:

1151

1152

1154 break;

1155 case TargetOpcode::G_VECREDUCE_SEQ_FADD:

1156 case TargetOpcode::G_VECREDUCE_SEQ_FMUL:

1157

1158

1160 break;

1161 case TargetOpcode::G_INTRINSIC:

1162 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: {

1164 case Intrinsic::aarch64_neon_fcvtas:

1165 case Intrinsic::aarch64_neon_fcvtau:

1166 case Intrinsic::aarch64_neon_fcvtzs:

1167 case Intrinsic::aarch64_neon_fcvtzu:

1168 case Intrinsic::aarch64_neon_fcvtms:

1169 case Intrinsic::aarch64_neon_fcvtmu:

1170 case Intrinsic::aarch64_neon_fcvtns:

1171 case Intrinsic::aarch64_neon_fcvtnu:

1172 case Intrinsic::aarch64_neon_fcvtps:

1173 case Intrinsic::aarch64_neon_fcvtpu: {

1175 if (MRI.getType(MI.getOperand(0).getReg()).isVector()) {

1177 break;

1178 }

1181 if (((DstSize == SrcSize) || STI.hasFeature(AArch64::FeatureFPRCVT)) &&

1182 all_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),

1184 return onlyUsesFP(UseMI, MRI, TRI) ||

1185 prefersFPUse(UseMI, MRI, TRI);

1186 }))

1188 else

1190 break;

1191 }

1192 case Intrinsic::aarch64_neon_vcvtfxs2fp:

1193 case Intrinsic::aarch64_neon_vcvtfxu2fp:

1194 case Intrinsic::aarch64_neon_vcvtfp2fxs:

1195 case Intrinsic::aarch64_neon_vcvtfp2fxu:

1196

1197

1198

1201

1202

1203 break;

1204 default: {

1205

1206

1207 unsigned Idx = 0;

1208 if (onlyDefinesFP(MI, MRI, TRI))

1209 for (const auto &Op : MI.defs()) {

1210 if (Op.isReg())

1212 ++Idx;

1213 }

1214 else

1215 Idx += MI.getNumExplicitDefs();

1216

1217 if (onlyUsesFP(MI, MRI, TRI))

1218 for (const auto &Op : MI.explicit_uses()) {

1219 if (Op.isReg())

1221 ++Idx;

1222 }

1223 break;

1224 }

1225 }

1226 break;

1227 }

1228 case TargetOpcode::G_LROUND:

1229 case TargetOpcode::G_LLROUND: {

1230

1232 break;

1233 }

1234 }

1235

1236

1238 for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {

1239 if (MI.getOperand(Idx).isReg() && MI.getOperand(Idx).getReg()) {

1240 LLT Ty = MRI.getType(MI.getOperand(Idx).getReg());

1241 if (!Ty.isValid())

1242 continue;

1243 auto Mapping =

1245 if (!Mapping->isValid())

1247

1248 OpdsMapping[Idx] = Mapping;

1249 }

1250 }

1251

1253 NumOperands);

1254}

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder & UseMI

MachineInstrBuilder MachineInstrBuilder & DefMI

static unsigned getIntrinsicID(const SDNode *N)

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

#define CHECK_VALUEMAP(RBName, Size)

static bool isFPIntrinsic(const MachineRegisterInfo &MRI, const MachineInstr &MI)

Definition AArch64RegisterBankInfo.cpp:452

#define CHECK_VALUEMAP_3OPS(RBName, Size)

static const unsigned CustomMappingID

Definition AArch64RegisterBankInfo.cpp:45

#define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB)

#define CHECK_VALUEMAP_CROSSREGCPY(RBNameDst, RBNameSrc, Size)

#define CHECK_VALUEMAP_FPEXT(DstSize, SrcSize)

This file declares the targeting of the RegisterBankInfo class for AArch64.

static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...

Implement a low-level type suitable for MachineInstr level instruction selection.

This file declares the MachineIRBuilder class.

static const MCPhysReg FPR[]

FPR - The set of FP registers that should be allocated for arguments on Darwin and AIX.

This file defines the SmallVector class.

static unsigned getRegBankBaseIdxOffset(unsigned RBIdx, TypeSize Size)

static const RegisterBankInfo::ValueMapping * getCopyMapping(unsigned DstBankID, unsigned SrcBankID, TypeSize Size)

Get the pointer to the ValueMapping of the operands of a copy instruction from the SrcBankID register...

static bool checkPartialMappingIdx(PartialMappingIdx FirstAlias, PartialMappingIdx LastAlias, ArrayRef< PartialMappingIdx > Order)

static const RegisterBankInfo::PartialMapping PartMappings[]

static const RegisterBankInfo::ValueMapping * getFPExtMapping(unsigned DstSize, unsigned SrcSize)

Get the instruction mapping for G_FPEXT.

static const RegisterBankInfo::ValueMapping * getValueMapping(PartialMappingIdx RBIdx, TypeSize Size)

Get the pointer to the ValueMapping representing the RegisterBank at RBIdx with a size of Size.

static const RegisterBankInfo::ValueMapping ValMappings[]

InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const override

Get the alternative mappings for MI.

Definition AArch64RegisterBankInfo.cpp:254

unsigned copyCost(const RegisterBank &A, const RegisterBank &B, TypeSize Size) const override

Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.

Definition AArch64RegisterBankInfo.cpp:221

const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override

Get a register bank that covers RC.

Definition AArch64RegisterBankInfo.cpp:243

AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)

Definition AArch64RegisterBankInfo.cpp:47

const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override

Get the mapping of the different operands of MI on the register bank.

Definition AArch64RegisterBankInfo.cpp:679

const AArch64RegisterInfo * getRegisterInfo() const override

static constexpr LLT scalar(unsigned SizeInBits)

Get a low-level scalar or aggregate "bag of bits".

constexpr bool isVector() const

constexpr TypeSize getSizeInBits() const

Returns the total size of the type. Must only be called on sized types.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Helper class to build MachineInstr.

MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)

Build and insert Res = G_ANYEXT Op0.

Get the register for the operand index.

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Helper class that represents how the value of an instruction may be mapped and what is the related co...

bool isValid() const

Check whether this object is valid.

virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const

Get the alternative mappings for MI.

const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const

Method to get a uniquely generated InstructionMapping.

static void applyDefaultMapping(const OperandsMapper &OpdMapper)

Helper method to apply something that is like the default mapping.

const InstructionMapping & getInvalidInstructionMapping() const

Method to get a uniquely generated invalid InstructionMapping.

const RegisterBank & getRegBank(unsigned ID)

Get the register bank identified by ID.

unsigned getMaximumSize(unsigned RegBankID) const

Get the maximum size in bits that fits in the given register bank.

TypeSize getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const

Get the size in bits of Reg.

virtual const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const

Get a register bank that covers RC.

const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const

Get the uniquely generated array of ValueMapping for the elements of between Begin and End.

static const unsigned DefaultMappingID

Identifier used when the related instruction mapping instance is generated by target independent code...

SmallVector< const InstructionMapping *, 4 > InstructionMappings

Convenient type to represent the alternatives for mapping an instruction.

virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, TypeSize Size) const

Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.

const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const

Try to get the mapping of MI.

This class implements the register bank concept.

LLVM_ABI bool covers(const TargetRegisterClass &RC) const

Check whether this register bank covers RC.

unsigned getID() const

Get the identifier of this register bank.

Wrapper class representing virtual and physical registers.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

unsigned getID() const

Return the register class ID number.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

TargetSubtargetInfo - Generic base class for all target subtargets.

virtual const TargetRegisterInfo * getRegisterInfo() const =0

Return the target's register information.

static constexpr TypeSize getFixed(ScalarTy ExactSize)

Type * getArrayElementType() const

bool isFPOrFPVectorTy() const

Return true if this is a FP type or a vector of FP.

iterator_range< user_iterator > users()

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

This is an optimization pass for GlobalISel generic memory operations.

FunctionAddr VTableAddr Value

bool all_of(R &&range, UnaryPredicate P)

Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

bool isPreISelGenericOpcode(unsigned Opcode)

Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.

bool isPreISelGenericOptimizationHint(unsigned Opcode)

bool any_of(R &&range, UnaryPredicate P)

Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.

bool isa(const From &Val)

isa - Return true if the parameter to the template is an instance of one of the template type argu...

DWARFExpression::Operation Op

void call_once(once_flag &flag, Function &&F, Args &&... ArgList)

Execute the function specified as a parameter once.

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

LLVM_ABI bool isPreISelGenericFloatingPointOpcode(unsigned Opc)

Returns whether opcode Opc is a pre-isel generic floating-point opcode, having only floating-point op...

The llvm::once_flag structure.