AMDHSAKernelDescriptor.h Source File (original) (raw)

31#define AMDHSA_BITS_ENUM_ENTRY(NAME, SHIFT, WIDTH) \

32 NAME ## _SHIFT = (SHIFT), \

33 NAME ## _WIDTH = (WIDTH), \

34 NAME = (((1 << (WIDTH)) - 1) << (SHIFT))

44#define AMDHSA_BITS_SET(DST, MSK, VAL) \

45 do { \

46 auto local = VAL; \

47 DST &= ~MSK; \

48 DST |= ((local << MSK##_SHIFT) & MSK); \

49 } while (0)

61};

69};

77};

81#define COMPUTE_PGM_RSRC1(NAME, SHIFT, WIDTH) \

82 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_##NAME, SHIFT, WIDTH)

84#define COMPUTE_PGM_RSRC1_GFX6_GFX8(NAME, SHIFT, WIDTH) \

85 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX6_GFX8_##NAME, SHIFT, WIDTH)

87#define COMPUTE_PGM_RSRC1_GFX6_GFX9(NAME, SHIFT, WIDTH) \

88 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX6_GFX9_##NAME, SHIFT, WIDTH)

90#define COMPUTE_PGM_RSRC1_GFX6_GFX11(NAME, SHIFT, WIDTH) \

91 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX6_GFX11_##NAME, SHIFT, WIDTH)

93#define COMPUTE_PGM_RSRC1_GFX6_GFX120(NAME, SHIFT, WIDTH) \

94 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX6_GFX120_##NAME, SHIFT, WIDTH)

96#define COMPUTE_PGM_RSRC1_GFX9_PLUS(NAME, SHIFT, WIDTH) \

97 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX9_PLUS_##NAME, SHIFT, WIDTH)

99#define COMPUTE_PGM_RSRC1_GFX10_PLUS(NAME, SHIFT, WIDTH) \

100 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX10_PLUS_##NAME, SHIFT, WIDTH)

101

102#define COMPUTE_PGM_RSRC1_GFX12_PLUS(NAME, SHIFT, WIDTH) \

103 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX12_PLUS_##NAME, SHIFT, WIDTH)

104

105#define COMPUTE_PGM_RSRC1_GFX125(NAME, SHIFT, WIDTH) \

106 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX125_##NAME, SHIFT, WIDTH)

107enum : int32_t {

132};

133#undef COMPUTE_PGM_RSRC1

134

135

136

137#define COMPUTE_PGM_RSRC2(NAME, SHIFT, WIDTH) \

138 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC2_##NAME, SHIFT, WIDTH)

139

140#define COMPUTE_PGM_RSRC2_GFX6_GFX11(NAME, SHIFT, WIDTH) \

141 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC2_GFX6_GFX11_##NAME, SHIFT, WIDTH)

142

143#define COMPUTE_PGM_RSRC2_GFX6_GFX120(NAME, SHIFT, WIDTH) \

144 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC2_GFX6_GFX120_##NAME, SHIFT, WIDTH)

145

146#define COMPUTE_PGM_RSRC2_GFX12_PLUS(NAME, SHIFT, WIDTH) \

147 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC2_GFX12_PLUS_##NAME, SHIFT, WIDTH)

148

149#define COMPUTE_PGM_RSRC2_GFX120(NAME, SHIFT, WIDTH) \

150 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC2_GFX120_##NAME, SHIFT, WIDTH)

151

152#define COMPUTE_PGM_RSRC2_GFX125(NAME, SHIFT, WIDTH) \

153 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC2_GFX125_##NAME, SHIFT, WIDTH)

154enum : int32_t {

168 COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION, 24, 1),

170 COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO, 26, 1),

172 COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW, 28, 1),

176};

177#undef COMPUTE_PGM_RSRC2

178

179

180

181#define COMPUTE_PGM_RSRC3_GFX90A(NAME, SHIFT, WIDTH) \

182 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX90A_ ## NAME, SHIFT, WIDTH)

183enum : int32_t {

188};

189#undef COMPUTE_PGM_RSRC3_GFX90A

190

191

192

193

194#define COMPUTE_PGM_RSRC3_GFX10_PLUS(NAME, SHIFT, WIDTH) \

195 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX10_PLUS_##NAME, SHIFT, WIDTH)

196

197#define COMPUTE_PGM_RSRC3_GFX10(NAME, SHIFT, WIDTH) \

198 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX10_##NAME, SHIFT, WIDTH)

199

200#define COMPUTE_PGM_RSRC3_GFX10_GFX11(NAME, SHIFT, WIDTH) \

201 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX10_GFX11_##NAME, SHIFT, WIDTH)

202

203#define COMPUTE_PGM_RSRC3_GFX10_GFX120(NAME, SHIFT, WIDTH) \

204 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX10_GFX120_##NAME, SHIFT, WIDTH)

205

206#define COMPUTE_PGM_RSRC3_GFX11_PLUS(NAME, SHIFT, WIDTH) \

207 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX11_PLUS_##NAME, SHIFT, WIDTH)

208

209#define COMPUTE_PGM_RSRC3_GFX11(NAME, SHIFT, WIDTH) \

210 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX11_##NAME, SHIFT, WIDTH)

211

212#define COMPUTE_PGM_RSRC3_GFX12_PLUS(NAME, SHIFT, WIDTH) \

213 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX12_PLUS_##NAME, SHIFT, WIDTH)

214

215#define COMPUTE_PGM_RSRC3_GFX125(NAME, SHIFT, WIDTH) \

216 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX125_##NAME, SHIFT, WIDTH)

217enum : int32_t {

236};

237#undef COMPUTE_PGM_RSRC3_GFX10_PLUS

238

239

240#define KERNEL_CODE_PROPERTY(NAME, SHIFT, WIDTH) \

241 AMDHSA_BITS_ENUM_ENTRY(KERNEL_CODE_PROPERTY_ ## NAME, SHIFT, WIDTH)

242enum : int32_t {

254};

255#undef KERNEL_CODE_PROPERTY

256

257

258#define KERNARG_PRELOAD_SPEC(NAME, SHIFT, WIDTH) \

259 AMDHSA_BITS_ENUM_ENTRY(KERNARG_PRELOAD_SPEC_##NAME, SHIFT, WIDTH)

260enum : int32_t {

263};

264#undef KERNARG_PRELOAD_SPEC

265

266

281

295};

296

297static_assert(

298 sizeof(kernel_descriptor_t) == 64,

299 "invalid size for kernel_descriptor_t");

300static_assert(offsetof(kernel_descriptor_t, group_segment_fixed_size) ==

302 "invalid offset for group_segment_fixed_size");

303static_assert(offsetof(kernel_descriptor_t, private_segment_fixed_size) ==

305 "invalid offset for private_segment_fixed_size");

306static_assert(offsetof(kernel_descriptor_t, kernarg_size) ==

308 "invalid offset for kernarg_size");

310 "invalid offset for reserved0");

311static_assert(offsetof(kernel_descriptor_t, kernel_code_entry_byte_offset) ==

313 "invalid offset for kernel_code_entry_byte_offset");

315 "invalid offset for reserved1");

316static_assert(offsetof(kernel_descriptor_t, compute_pgm_rsrc3) ==

318 "invalid offset for compute_pgm_rsrc3");

319static_assert(offsetof(kernel_descriptor_t, compute_pgm_rsrc1) ==

321 "invalid offset for compute_pgm_rsrc1");

322static_assert(offsetof(kernel_descriptor_t, compute_pgm_rsrc2) ==

324 "invalid offset for compute_pgm_rsrc2");

325static_assert(offsetof(kernel_descriptor_t, kernel_code_properties) ==

327 "invalid offset for kernel_code_properties");

328static_assert(offsetof(kernel_descriptor_t, kernarg_preload) ==

330 "invalid offset for kernarg_preload");

332 "invalid offset for reserved3");

333

334}