LLVM: include/llvm/Support/AMDHSAKernelDescriptor.h File Reference (original) (raw)

AMDHSA kernel descriptor definitions. More...

#include <cstddef>
#include <cstdint>

Go to the source code of this file.

Namespaces
namespace llvm
This is an optimization pass for GlobalISel generic memory operations.
namespace llvm::amdhsa
Macros
#define AMDHSA_BITS_ENUM_ENTRY(NAME, SHIFT, WIDTH)
#define AMDHSA_BITS_GET(SRC, MSK)
#define AMDHSA_BITS_SET(DST, MSK, VAL)
#define COMPUTE_PGM_RSRC1(NAME, SHIFT, WIDTH)
#define COMPUTE_PGM_RSRC1_GFX6_GFX8(NAME, SHIFT, WIDTH)
#define COMPUTE_PGM_RSRC1_GFX6_GFX9(NAME, SHIFT, WIDTH)
#define COMPUTE_PGM_RSRC1_GFX6_GFX11(NAME, SHIFT, WIDTH)
#define COMPUTE_PGM_RSRC1_GFX6_GFX120(NAME, SHIFT, WIDTH)
#define COMPUTE_PGM_RSRC1_GFX9_PLUS(NAME, SHIFT, WIDTH)
#define COMPUTE_PGM_RSRC1_GFX10_PLUS(NAME, SHIFT, WIDTH)
#define COMPUTE_PGM_RSRC1_GFX12_PLUS(NAME, SHIFT, WIDTH)
#define COMPUTE_PGM_RSRC1_GFX125(NAME, SHIFT, WIDTH)
#define COMPUTE_PGM_RSRC2(NAME, SHIFT, WIDTH)
#define COMPUTE_PGM_RSRC2_GFX6_GFX11(NAME, SHIFT, WIDTH)
#define COMPUTE_PGM_RSRC2_GFX6_GFX120(NAME, SHIFT, WIDTH)
#define COMPUTE_PGM_RSRC2_GFX12_PLUS(NAME, SHIFT, WIDTH)
#define COMPUTE_PGM_RSRC2_GFX120(NAME, SHIFT, WIDTH)
#define COMPUTE_PGM_RSRC2_GFX125(NAME, SHIFT, WIDTH)
#define COMPUTE_PGM_RSRC3_GFX90A(NAME, SHIFT, WIDTH)
#define COMPUTE_PGM_RSRC3_GFX10_PLUS(NAME, SHIFT, WIDTH)
#define COMPUTE_PGM_RSRC3_GFX10(NAME, SHIFT, WIDTH)
#define COMPUTE_PGM_RSRC3_GFX10_GFX11(NAME, SHIFT, WIDTH)
#define COMPUTE_PGM_RSRC3_GFX10_GFX120(NAME, SHIFT, WIDTH)
#define COMPUTE_PGM_RSRC3_GFX11_PLUS(NAME, SHIFT, WIDTH)
#define COMPUTE_PGM_RSRC3_GFX11(NAME, SHIFT, WIDTH)
#define COMPUTE_PGM_RSRC3_GFX12_PLUS(NAME, SHIFT, WIDTH)
#define COMPUTE_PGM_RSRC3_GFX125(NAME, SHIFT, WIDTH)
#define KERNEL_CODE_PROPERTY(NAME, SHIFT, WIDTH)
#define KERNARG_PRELOAD_SPEC(NAME, SHIFT, WIDTH)
Enumerations
enum : uint8_t { llvm::amdhsa::FLOAT_ROUND_MODE_NEAR_EVEN = 0 , llvm::amdhsa::FLOAT_ROUND_MODE_PLUS_INFINITY = 1 , llvm::amdhsa::FLOAT_ROUND_MODE_MINUS_INFINITY = 2 , llvm::amdhsa::FLOAT_ROUND_MODE_ZERO = 3 }
enum : uint8_t { llvm::amdhsa::FLOAT_DENORM_MODE_FLUSH_SRC_DST = 0 , llvm::amdhsa::FLOAT_DENORM_MODE_FLUSH_DST = 1 , llvm::amdhsa::FLOAT_DENORM_MODE_FLUSH_SRC = 2 , llvm::amdhsa::FLOAT_DENORM_MODE_FLUSH_NONE = 3 }
enum : uint8_t { llvm::amdhsa::SYSTEM_VGPR_WORKITEM_ID_X = 0 , llvm::amdhsa::SYSTEM_VGPR_WORKITEM_ID_X_Y = 1 , llvm::amdhsa::SYSTEM_VGPR_WORKITEM_ID_X_Y_Z = 2 , llvm::amdhsa::SYSTEM_VGPR_WORKITEM_ID_UNDEFINED = 3 }
enum : int32_t { llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6) , llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6) , llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6) , llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6) , llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6) , llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6) , llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6) , llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6) , llvm::amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11 =(ENABLE_DX10_CLAMP, 21, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC1_GFX12_PLUS =(ENABLE_WG_RR_EN, 21, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6) , llvm::amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11 =(ENABLE_DX10_CLAMP, 21, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC1_GFX12_PLUS =(ENABLE_WG_RR_EN, 21, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6) , llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6) , llvm::amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX8 =(RESERVED0, 26, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC1_GFX9_PLUS =(FP16_OVFL, 26, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX120 =(RESERVED1, 27, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC1_GFX125 =(FLAT_SCRATCH_IS_NV, 27, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6) , llvm::amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX9 =(RESERVED3, 29, 3) , llvm::amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS =(WGP_MODE, 29, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS =(WGP_MODE, 29, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS =(WGP_MODE, 29, 1) }
enum : int32_t { llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC2_GFX6_GFX120 =(USER_SGPR_COUNT, 1, 5) , llvm::amdhsa::COMPUTE_PGM_RSRC2_GFX6_GFX11 =(ENABLE_TRAP_HANDLER, 6, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC2_GFX120 =(ENABLE_DYNAMIC_VGPR, 6, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC2_GFX125 =(USER_SGPR_COUNT, 1, 6) , llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1) }
enum : int32_t { llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX90A =(ACCUM_OFFSET, 0, 6) , llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX90A =(ACCUM_OFFSET, 0, 6) , llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX90A =(ACCUM_OFFSET, 0, 6) , llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX90A =(ACCUM_OFFSET, 0, 6) }
enum : int32_t { llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX10_GFX11 =(SHARED_VGPR_COUNT, 0, 4) , llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX12_PLUS =(RESERVED0, 0, 4) , llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX10 =(RESERVED1, 4, 8) , llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX11 =(INST_PREF_SIZE, 4, 6) , llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX11 =(INST_PREF_SIZE, 4, 6) , llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX11 =(INST_PREF_SIZE, 4, 6) , llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX12_PLUS =(RESERVED0, 0, 4) , llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX10_PLUS =(RESERVED2, 12, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX10_GFX11 =(SHARED_VGPR_COUNT, 0, 4) , llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX12_PLUS =(RESERVED0, 0, 4) , llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX10_GFX120 =(RESERVED4, 14, 8) , llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX125 =(NAMED_BAR_CNT, 14, 3) , llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX125 =(NAMED_BAR_CNT, 14, 3) , llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX125 =(NAMED_BAR_CNT, 14, 3) , llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX125 =(NAMED_BAR_CNT, 14, 3) , llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX10_PLUS =(RESERVED2, 12, 1) , llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX10 =(RESERVED1, 4, 8) , llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX11_PLUS =(IMAGE_OP, 31, 1) }
enum : int32_t { llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1) , llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1) , llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1) , llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1) , llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1) , llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1) , llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1) , llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1) , llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1) , llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1) , llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1) }
enum : int32_t { llvm::amdhsa::KERNARG_PRELOAD_SPEC =(LENGTH, 0, 7) , llvm::amdhsa::KERNARG_PRELOAD_SPEC =(LENGTH, 0, 7) }
enum : uint32_t { llvm::amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET = 0 , llvm::amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET = 4 , llvm::amdhsa::KERNARG_SIZE_OFFSET = 8 , llvm::amdhsa::RESERVED0_OFFSET = 12 , llvm::amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET = 16 , llvm::amdhsa::RESERVED1_OFFSET = 24 , llvm::amdhsa::COMPUTE_PGM_RSRC3_OFFSET = 44 , llvm::amdhsa::COMPUTE_PGM_RSRC1_OFFSET = 48 , llvm::amdhsa::COMPUTE_PGM_RSRC2_OFFSET = 52 , llvm::amdhsa::KERNEL_CODE_PROPERTIES_OFFSET = 56 , llvm::amdhsa::KERNARG_PRELOAD_OFFSET = 58 , llvm::amdhsa::RESERVED3_OFFSET = 60 }

AMDHSA kernel descriptor definitions.

For more information, visit https://llvm.org/docs/AMDGPUUsage.html#kernel-descriptor

Warning

Any changes to this file should also be audited for corresponding changes needed in both the assembler and disassembler, namely:

Definition in file AMDHSAKernelDescriptor.h.

◆ AMDHSA_BITS_ENUM_ENTRY

#define AMDHSA_BITS_ENUM_ENTRY ( NAME,
SHIFT,
WIDTH )

Value:

NAME ## _SHIFT = (SHIFT), \

NAME ## _WIDTH = (WIDTH), \

NAME = (((1 << (WIDTH)) - 1) << (SHIFT))

Definition at line 31 of file AMDHSAKernelDescriptor.h.

◆ AMDHSA_BITS_GET

#define AMDHSA_BITS_GET ( SRC,
MSK )

◆ AMDHSA_BITS_SET

#define AMDHSA_BITS_SET ( DST,
MSK,
VAL )

Value:

do { \

auto local = VAL; \

DST &= ~MSK; \

DST |= ((local << MSK##_SHIFT) & MSK); \

} while (0)

Definition at line 44 of file AMDHSAKernelDescriptor.h.

◆ COMPUTE_PGM_RSRC1

#define COMPUTE_PGM_RSRC1 ( NAME,
SHIFT,
WIDTH )

Value:

AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_##NAME, SHIFT, WIDTH)

#define AMDHSA_BITS_ENUM_ENTRY(NAME, SHIFT, WIDTH)

Definition at line 81 of file AMDHSAKernelDescriptor.h.

◆ COMPUTE_PGM_RSRC1_GFX10_PLUS

#define COMPUTE_PGM_RSRC1_GFX10_PLUS ( NAME,
SHIFT,
WIDTH )

◆ COMPUTE_PGM_RSRC1_GFX125

#define COMPUTE_PGM_RSRC1_GFX125 ( NAME,
SHIFT,
WIDTH )

◆ COMPUTE_PGM_RSRC1_GFX12_PLUS

#define COMPUTE_PGM_RSRC1_GFX12_PLUS ( NAME,
SHIFT,
WIDTH )

◆ COMPUTE_PGM_RSRC1_GFX6_GFX11

#define COMPUTE_PGM_RSRC1_GFX6_GFX11 ( NAME,
SHIFT,
WIDTH )

◆ COMPUTE_PGM_RSRC1_GFX6_GFX120

#define COMPUTE_PGM_RSRC1_GFX6_GFX120 ( NAME,
SHIFT,
WIDTH )

◆ COMPUTE_PGM_RSRC1_GFX6_GFX8

#define COMPUTE_PGM_RSRC1_GFX6_GFX8 ( NAME,
SHIFT,
WIDTH )

◆ COMPUTE_PGM_RSRC1_GFX6_GFX9

#define COMPUTE_PGM_RSRC1_GFX6_GFX9 ( NAME,
SHIFT,
WIDTH )

◆ COMPUTE_PGM_RSRC1_GFX9_PLUS

#define COMPUTE_PGM_RSRC1_GFX9_PLUS ( NAME,
SHIFT,
WIDTH )

◆ COMPUTE_PGM_RSRC2

#define COMPUTE_PGM_RSRC2 ( NAME,
SHIFT,
WIDTH )

◆ COMPUTE_PGM_RSRC2_GFX120

#define COMPUTE_PGM_RSRC2_GFX120 ( NAME,
SHIFT,
WIDTH )

◆ COMPUTE_PGM_RSRC2_GFX125

#define COMPUTE_PGM_RSRC2_GFX125 ( NAME,
SHIFT,
WIDTH )

◆ COMPUTE_PGM_RSRC2_GFX12_PLUS

#define COMPUTE_PGM_RSRC2_GFX12_PLUS ( NAME,
SHIFT,
WIDTH )

◆ COMPUTE_PGM_RSRC2_GFX6_GFX11

#define COMPUTE_PGM_RSRC2_GFX6_GFX11 ( NAME,
SHIFT,
WIDTH )

◆ COMPUTE_PGM_RSRC2_GFX6_GFX120

#define COMPUTE_PGM_RSRC2_GFX6_GFX120 ( NAME,
SHIFT,
WIDTH )

◆ COMPUTE_PGM_RSRC3_GFX10

#define COMPUTE_PGM_RSRC3_GFX10 ( NAME,
SHIFT,
WIDTH )

◆ COMPUTE_PGM_RSRC3_GFX10_GFX11

#define COMPUTE_PGM_RSRC3_GFX10_GFX11 ( NAME,
SHIFT,
WIDTH )

◆ COMPUTE_PGM_RSRC3_GFX10_GFX120

#define COMPUTE_PGM_RSRC3_GFX10_GFX120 ( NAME,
SHIFT,
WIDTH )

◆ COMPUTE_PGM_RSRC3_GFX10_PLUS

#define COMPUTE_PGM_RSRC3_GFX10_PLUS ( NAME,
SHIFT,
WIDTH )

◆ COMPUTE_PGM_RSRC3_GFX11

#define COMPUTE_PGM_RSRC3_GFX11 ( NAME,
SHIFT,
WIDTH )

◆ COMPUTE_PGM_RSRC3_GFX11_PLUS

#define COMPUTE_PGM_RSRC3_GFX11_PLUS ( NAME,
SHIFT,
WIDTH )

◆ COMPUTE_PGM_RSRC3_GFX125

#define COMPUTE_PGM_RSRC3_GFX125 ( NAME,
SHIFT,
WIDTH )

◆ COMPUTE_PGM_RSRC3_GFX12_PLUS

#define COMPUTE_PGM_RSRC3_GFX12_PLUS ( NAME,
SHIFT,
WIDTH )

◆ COMPUTE_PGM_RSRC3_GFX90A

#define COMPUTE_PGM_RSRC3_GFX90A ( NAME,
SHIFT,
WIDTH )

◆ KERNARG_PRELOAD_SPEC

#define KERNARG_PRELOAD_SPEC ( NAME,
SHIFT,
WIDTH )

◆ KERNEL_CODE_PROPERTY

#define KERNEL_CODE_PROPERTY ( NAME,
SHIFT,
WIDTH )