LLVM: lib/Target/ARM/ARMISelDAGToDAG.cpp File Reference (original) (raw)

Go to the source code of this file.

Functions
static bool isInt32Immediate (SDNode *N, unsigned &Imm)
isInt32Immediate - This method tests to see if the node is a 32-bit constant operand.
static bool isInt32Immediate (SDValue N, unsigned &Imm)
static bool isOpcWithIntImmediate (SDNode *N, unsigned Opc, unsigned &Imm)
static bool isScaledConstantInRange (SDValue Node, int Scale, int RangeMin, int RangeMax, int &ScaledConstant)
Check whether a particular node is a constant value representable as (N * Scale) where (N in [RangeMin, RangeMax).
static bool shouldUseZeroOffsetLdSt (SDValue N)
static SDValue getAL (SelectionDAG *CurDAG, const SDLoc &dl)
getAL - Returns a ARMCC::AL immediate node.
static bool isVLDfixed (unsigned Opc)
static bool isVSTfixed (unsigned Opc)
static unsigned getVLDSTRegisterUpdateOpcode (unsigned Opc)
static bool isPerfectIncrement (SDValue Inc, EVT VecTy, unsigned NumVecs)
Returns true if the given increment is a Constant known to be equal to the access size performed by a NEON load/store.
static bool SDValueToConstBool (SDValue SDVal)
static std::optional< std::pair< unsigned, unsigned > > getContiguousRangeOfSetBits (const APInt &A)
static unsigned getVectorShuffleOpcode (EVT VT, unsigned Opc64[3], unsigned Opc128[3])
static void getIntOperandsFromRegisterString (StringRef RegString, SelectionDAG *CurDAG, const SDLoc &DL, std::vector< SDValue > &Ops)
static int getBankedRegisterMask (StringRef RegString)
static int getMClassFlagsMask (StringRef Flags)
static int getMClassRegisterMask (StringRef Reg, const ARMSubtarget *Subtarget)
static int getARClassRegisterMask (StringRef Reg, StringRef Flags)
Variables
static cl::opt< bool > DisableShifterOp ("disable-shifter-op", cl::Hidden, cl::desc("Disable isel of shifter-op"), cl::init(false))

◆ DEBUG_TYPE

#define DEBUG_TYPE "arm-isel"

◆ PASS_NAME

◆ getAL()

◆ getARClassRegisterMask()

◆ getBankedRegisterMask()

int getBankedRegisterMask ( StringRef RegString) inlinestatic

◆ getContiguousRangeOfSetBits()

◆ getIntOperandsFromRegisterString()

◆ getMClassFlagsMask()

int getMClassFlagsMask ( StringRef Flags) inlinestatic

◆ getMClassRegisterMask()

◆ getVectorShuffleOpcode()

◆ getVLDSTRegisterUpdateOpcode()

◆ isInt32Immediate() [1/2]

◆ isInt32Immediate() [2/2]

◆ isOpcWithIntImmediate()

◆ isPerfectIncrement()

◆ isScaledConstantInRange()

bool isScaledConstantInRange ( SDValue Node, int Scale, int RangeMin, int RangeMax, int & ScaledConstant ) static

◆ isVLDfixed()

◆ isVSTfixed()

◆ SDValueToConstBool()

◆ shouldUseZeroOffsetLdSt()

◆ DisableShifterOp

cl::opt< bool > DisableShifterOp("disable-shifter-op", cl::Hidden, cl::desc("Disable isel of shifter-op"), cl::init(false)) ( "disable-shifter-op" , cl::Hidden , cl::desc("Disable isel of shifter-op") , cl::init(false) ) static