ARMISelLowering.h Source File (original) (raw)

14#ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H

15#define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H

32#include

33#include

35namespace llvm {

54 namespace ARM {

75 }

78 namespace ARM {

82 }

89 enum ByValCopyKind {

91 NoCopy,

94 CopyOnce,

98 CopyViaTemp,

99 };

100

101 public:

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126 EVT VT) const override;

127

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140

148

150 const APInt &OriginalDemandedBits,

151 const APInt &OriginalDemandedElts,

153 TargetLoweringOpt &TLO,

154 unsigned Depth) const override;

155

157

158

159

160

164 unsigned *Fast) const override;

165

167 const AttributeList &FuncAttributes) const override;

168

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184 Type *Ty, unsigned AS,

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220 const APInt &DemandedElts,

222 unsigned Depth) const override;

223

225 const APInt &DemandedElts,

226 TargetLoweringOpt &TLO) const override;

227

229

230

231

233 AsmOperandInfo &info, const char *constraint) const override;

234

235 std::pair<unsigned, const TargetRegisterClass *>

237 StringRef Constraint, MVT VT) const override;

238

240

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242

243

244

246 std::vector &Ops,

248

251 if (ConstraintCode == "Q")

253 if (ConstraintCode.size() == 2) {

254 if (ConstraintCode[0] == 'U') {

255 switch(ConstraintCode[1]) {

256 default:

257 break;

258 case 'm':

260 case 'n':

262 case 'q':

264 case 's':

266 case 't':

268 case 'v':

270 case 'y':

272 }

273 }

274 }

276 }

277

279 return Subtarget;

280 }

281

282

283

286

288 Align &PrefAlign) const override;

289

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302

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305 return V.getValueType().isScalarInteger();

306 }

307

308 bool

311

312

313

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316 bool ForCodeSize = false) const override;

317

320 unsigned Intrinsic) const override;

321

322

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325 Type *Ty) const override;

326

327

328

330 unsigned Index) const override;

331

333 bool MathUsed) const override {

334

336 }

337

339 return Opc != ISD::VECREDUCE_ADD;

340 }

341

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363

364 void

366

371

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377 const APInt &GapMask) const override;

380 const APInt &GapMask) const override;

381

391

393

395

397 unsigned &Cost) const override;

398

401 bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const override;

402

408

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424

426 return HasStandaloneRem;

427 }

428

431 unsigned ExpansionFactor) const override;

432

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444 SDValue ConstNode) const override;

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468 EVT VT = Y.getValueType();

469

471 return false;

472

474 }

475

477 unsigned SelectOpcode, SDValue X,

479

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497 protected:

498 std::pair<const TargetRegisterClass *, uint8_t>

500 MVT VT) const override;

501

502 private:

503

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512

513 bool InsertFencesForAtomic;

514

515 bool HasStandaloneRem = true;

516

517 void addTypeForNEON(MVT VT, MVT PromotedLdStVT);

518 void addDRTypeForNEON(MVT VT);

519 void addQRTypeForNEON(MVT VT);

521

523

525 SDValue &Arg, RegsToPassVector &RegsToPass,

529 bool IsTailCall,

530 int SPDiff) const;

533 const SDLoc &dl) const;

534

536 bool isVarArg) const;

538 bool isVarArg) const;

539 std::pair<SDValue, MachinePointerInfo>

542 bool IsTailCall, int SPDiff) const;

609

612

615

616 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,

617 EVT VT) const override;

618

623

625

631 SDValue ThisVal, bool isCmseNSCall) const;

632

633 void initializeSplitCSR(MachineBasicBlock *Entry) const override;

634 void insertCopiesSplitCSR(

637

638 bool splitValueIntoRegisterParts(

640 unsigned NumParts, MVT PartVT, std::optionalCallingConv::ID CC)

641 const override;

642

643 SDValue joinRegisterPartsIntoValue(

645 unsigned NumParts, MVT PartVT, EVT ValueVT,

646 std::optionalCallingConv::ID CC) const override;

647

653

656 unsigned InRegsParamRecordIdx, int ArgOffset,

657 unsigned ArgSize) const;

658

661 unsigned ArgOffset, unsigned TotalArgRegsSaveSize,

662 bool ForceMutable = false) const;

663

666

667

668 void HandleByVal(CCState *, unsigned &, Align) const override;

669

670

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673 bool IsEligibleForTailCallOptimization(

676

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687 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;

688

689 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;

690

692

693 bool isUnsupportedFloatingType(EVT VT) const;

694

696

698 SDValue ARMcc, SDValue Flags, SelectionDAG &DAG) const;

700 SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;

702 const SDLoc &dl, bool Signaling = false) const;

703

704 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;

705

706 void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,

707 MachineBasicBlock *DispatchBB, int FI) const;

708

709 void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const;

710

711 MachineBasicBlock *EmitStructByval(MachineInstr &MI,

712 MachineBasicBlock *MBB) const;

713

714 MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI,

715 MachineBasicBlock *MBB) const;

716 MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI,

717 MachineBasicBlock *MBB) const;

718 void addMVEVectorTypes(bool HasMVEFP);

719 void addAllExtLoads(const MVT From, const MVT To, LegalizeAction Action);

720 void setAllExpand(MVT VT);

721 };

722

729

730 namespace ARM {

731

732 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,

733 const TargetLibraryInfo *libInfo);

734

735 }

736

737}

738

739#endif

static SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG)

const TargetInstrInfo & TII

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

MachineBasicBlock MachineBasicBlock::iterator MBBI

Function Alias Analysis Results

This file contains the simple types necessary to represent the attributes associated with functions a...

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

Analysis containing CSE Info

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

PowerPC Reduce CR logical Operation

This file defines the SmallVector class.

static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)

static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)

static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)

static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad, bool isV9, bool is64Bit)

static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad, bool isV9, bool is64Bit)

static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)

static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")

static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")

This file describes how to lower LLVM code to machine code.

static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG)

static SDValue LowerABS(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)

static SDValue LowerCallResult(SDValue Chain, SDValue InGlue, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)

LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...

Class for arbitrary precision integers.

bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT, unsigned SelectOpcode, SDValue X, SDValue Y) const override

Return true if pulling a binary operation into a select with an identity constant is profitable.

bool isReadOnly(const GlobalValue *GV) const

unsigned getMaxSupportedInterleaveFactor() const override

Get the maximum supported factor for interleaved memory accesses.

TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override

Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.

unsigned getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL) const

Returns the number of interleaved accesses that will be generated when lowering accesses of the given...

bool shouldInsertFencesForAtomic(const Instruction *I) const override

Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.

Align getABIAlignmentForCallingConv(Type *ArgTy, const DataLayout &DL) const override

Return the correct alignment for the current calling convention.

bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override

Return true if it is profitable to move this shift by a constant amount through its operand,...

If a physical register, this returns the register that receives the exception address on entry to an ...

ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override

Examine constraint string and operand type and determine a weight value.

bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...

const ARMSubtarget * getSubtarget() const

Definition ARMISelLowering.h:278

bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const

bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const

Returns true if the addressing mode representing by AM is legal for the Thumb1 target,...

bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override

getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mod...

bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallBase &I, MachineFunction &MF, unsigned Intrinsic) const override

getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes.

MachineInstr * EmitKCFICheck(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator &MBBI, const TargetInstrInfo *TII) const override

InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const override

Definition ARMISelLowering.h:250

bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize, Align &PrefAlign) const override

Return true if the pointer arguments to CI should be aligned by aligning the object whose address is ...

void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...

void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override

bool isMulAddWithConstProfitable(SDValue AddNode, SDValue ConstNode) const override

Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x,...

bool isLegalAddImmediate(int64_t Imm) const override

isLegalAddImmediate - Return true if the specified immediate is legal add immediate,...

EVT getOptimalMemOpType(LLVMContext &Context, const MemOp &Op, const AttributeList &FuncAttributes) const override

Returns the target specific optimal type for load and store operations as a result of memset,...

Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override

bool supportSwiftError() const override

Return true if the target supports swifterror attribute.

Definition ARMISelLowering.h:416

bool isFNegFree(EVT VT) const override

Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...

void finalizeLowering(MachineFunction &MF) const override

Execute target specific actions to finalize target lowering.

SDValue PerformMVETruncCombine(SDNode *N, DAGCombinerInfo &DCI) const

bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize=false) const override

isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively.

ConstraintType getConstraintType(StringRef Constraint) const override

getConstraintType - Given a constraint letter, return the type of constraint it is for this target.

bool preferIncOfAddToSubOfNot(EVT VT) const override

These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR...

bool useFPRegsForHalfType() const override

Definition ARMISelLowering.h:495

void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override

Determine which of the bits specified in Mask are known to be either zero or one and return them in t...

TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override

Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.

void insertSSPDeclarations(Module &M) const override

Inserts necessary declarations for SSP (stack protection) purpose.

SDValue PerformIntrinsicCombine(SDNode *N, DAGCombinerInfo &DCI) const

PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.

bool shouldFoldConstantShiftPairToMask(const SDNode *N) const override

Return true if it is profitable to fold a pair of shifts into a mask.

bool isDesirableToCommuteXorWithShift(const SDNode *N) const override

Return true if it is profitable to combine an XOR of a logical shift to create a logical shift of NOT...

SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const

PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.

Value * createComplexDeinterleavingIR(IRBuilderBase &B, ComplexDeinterleavingOperation OperationType, ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB, Value *Accumulator=nullptr) const override

Create the IR node for the given complex deinterleaving operation.

bool isComplexDeinterleavingSupported() const override

Does this target support complex deinterleaving.

bool supportSplitCSR(MachineFunction *MF) const override

Return true if the target supports that a subset of CSRs for the given machine function is handled ex...

Definition ARMISelLowering.h:420

SDValue PerformMVEExtCombine(SDNode *N, DAGCombinerInfo &DCI) const

bool SimplifyDemandedBitsForTargetNode(SDValue Op, const APInt &OriginalDemandedBits, const APInt &OriginalDemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth) const override

Attempt to simplify any target nodes based on the demanded bits/elts, returning true on success.

EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override

getSetCCResultType - Return the value type to use for ISD::SETCC.

MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override

This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...

Value * emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override

Perform a store-conditional operation to Addr.

SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override

This callback is invoked for operations that are unsupported by the target, which are registered to u...

CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const

FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override

createFastISel - This method returns a target specific FastISel object, or null if the target does no...

void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override

This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.

TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.

bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override

Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.

bool isTruncateFree(Type *SrcTy, Type *DstTy) const override

Return true if it's free to truncate a value of type FromTy to type ToTy.

bool isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override

isShuffleMaskLegal - Targets can use this to indicate that they only support some VECTOR_SHUFFLE oper...

bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override

Returns true if it is beneficial to convert a load of a constant to just the constant itself.

bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override

Try to convert math with an overflow comparison into the corresponding DAG node operation.

Definition ARMISelLowering.h:332

bool lowerInterleavedStore(Instruction *Store, Value *Mask, ShuffleVectorInst *SVI, unsigned Factor, const APInt &GapMask) const override

Lower an interleaved store into a vstN intrinsic.

bool canCreateUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const override

Return true if Op can create undef or poison from non-undef & non-poison operands.

bool isSelectSupported(SelectSupportKind Kind) const override

Definition ARMISelLowering.h:117

const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const override

getRegClassFor - Return the register class that should be used for the specified value type.

bool useLoadStackGuardNode(const Module &M) const override

If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...

bool lowerInterleavedLoad(Instruction *Load, Value *Mask, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor, const APInt &GapMask) const override

Lower an interleaved load into a vldN intrinsic.

std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const override

Return the largest legal super-reg register class of the register class for the specified type and it...

bool preferSelectsOverBooleanArithmetic(EVT VT) const override

Should we prefer selects to doing arithmetic on boolean types.

bool isZExtFree(SDValue Val, EVT VT2) const override

Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...

bool isCheapToSpeculateCttz(Type *Ty) const override

Return true if it is cheap to speculate a call to intrinsic cttz.

bool shouldReassociateReduction(unsigned Opc, EVT VT) const override

Definition ARMISelLowering.h:338

SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override

This method will be invoked for all target nodes and for any target-independent nodes that the target...

bool convertSetCCLogicToBitwiseLogic(EVT VT) const override

Use bitwise logic to make pairs of compares more efficient.

Definition ARMISelLowering.h:412

bool isCheapToSpeculateCtlz(Type *Ty) const override

Return true if it is cheap to speculate a call to intrinsic ctlz.

bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override

ARMTargetLowering(const TargetMachine &TM, const ARMSubtarget &STI)

bool isComplexDeinterleavingOperationSupported(ComplexDeinterleavingOperation Operation, Type *Ty) const override

Does this target support complex deinterleaving with the given operation and type.

bool supportKCFIBundles() const override

Return true if the target supports kcfi operand bundles.

SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const

PerformBRCONDCombine - Target-specific DAG combining for ARMISD::BRCOND.

If a physical register, this returns the register that receives the exception typeid on entry to a la...

Type * shouldConvertSplatType(ShuffleVectorInst *SVI) const override

Given a shuffle vector SVI representing a vector splat, return a new scalar type of size equal to SVI...

Value * emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const override

Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.

Instruction * makeDMB(IRBuilderBase &Builder, ARM_MB::MemBOpt Domain) const

bool isLegalICmpImmediate(int64_t Imm) const override

isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate,...

const char * LowerXConstraint(EVT ConstraintVT) const override

Try to replace an X constraint, which matches anything, with another that has more specific requireme...

unsigned getJumpTableEncoding() const override

Return the entry encoding for a jump table in the current function.

bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override

Return true if it is profitable for dag combiner to transform a floating point op of specified opcode...

TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.

CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const

bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const override

allowsMisalignedMemoryAccesses - Returns true if the target allows unaligned memory accesses of the s...

bool isLegalInterleavedAccessType(unsigned Factor, FixedVectorType *VecTy, Align Alignment, const DataLayout &DL) const

Returns true if VecTy is a legal interleaved access type.

bool isVectorLoadExtDesirable(SDValue ExtVal) const override

Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.

bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const override

Return true if the target can combine store(extractelement VectorTy,Idx).

bool preferZeroCompareBranch() const override

Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.

Definition ARMISelLowering.h:297

bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const MachineFunction &MF) const override

Returns if it's reasonable to merge stores to MemVT size.

Definition ARMISelLowering.h:403

bool useSoftFloat() const override

bool alignLoopsWithOptSize() const override

Should loops be aligned even when the function is marked OptSize (but not MinSize).

SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const

bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override

Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...

void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override

LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.

bool hasAndNotCompare(SDValue V) const override

Return true if the target should transform: (X & Y) == Y ---> (~X & Y) == 0 (X & Y) !...

Definition ARMISelLowering.h:303

std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override

Given a physical register constraint (e.g.

bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override

Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) satur...

bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const override

Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calli...

bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override

Return true if folding a constant offset with the given GlobalAddress is legal.

bool shouldFoldMaskToVariableShiftPair(SDValue Y) const override

Return true if it is profitable to fold a pair of shifts into a mask.

Definition ARMISelLowering.h:467

const ARMBaseTargetMachine & getTM() const

bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override

Return if the target supports combining a chain like:

bool softPromoteHalfType() const override

Definition ARMISelLowering.h:493

bool hasStandaloneRem(EVT VT) const override

Return true if the target can handle a standalone remainder operation.

Definition ARMISelLowering.h:425

ShiftLegalizationStrategy preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const override

bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override

getPostIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mo...

Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override

Inserts in the IR a target-specific intrinsic specifying a fence.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

An instruction that atomically checks whether a specified value is in a memory location,...

an instruction that atomically reads a memory location, combines it with another value,...

CCState - This class holds information needed while lowering arguments and return values.

CCValAssign - Represent assignment of one arg/retval to a location.

Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...

This class represents a function call, abstracting a target machine's calling convention.

This is an important base class in LLVM.

A parsed version of the target data layout string in and methods for querying it.

This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...

Class to represent fixed width SIMD vectors.

FunctionLoweringInfo - This contains information that is global to a function that is used when lower...

CallingConv::ID getCallingConv() const

getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...

bool hasFnAttribute(Attribute::AttrKind Kind) const

Return true if the function has the attribute.

Common base class shared among various IRBuilders.

Itinerary data supplied by a subtarget to be used by a target.

This is an important class for using LLVM in a threaded context.

An instruction for reading from memory.

Instructions::iterator instr_iterator

Function & getFunction()

Return the LLVM function that this machine code represents.

Representation of each machine instruction.

Flags

Flags values. These may be or'd together.

A Module instance is used to store all the information related to an LLVM module.

Wrapper class representing virtual and physical registers.

Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...

Represents one node in the SelectionDAG.

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...

This instruction constructs a fixed permutation of two input vectors.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

An instruction for storing to memory.

StringRef - Represent a constant reference to a string, i.e.

constexpr size_t size() const

size - Get the string size.

TargetInstrInfo - Interface to description of machine instruction set.

Provides information about what library functions are available for the current target.

virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const

Try to convert math with an overflow comparison into the corresponding DAG node operation.

ShiftLegalizationStrategy

Return the preferred strategy to legalize tihs SHIFT instruction, with ExpansionFactor being the recu...

SelectSupportKind

Enum that describes what type of support for selects the target has.

Sched::Preference getSchedulingPreference() const

Return target scheduling preference.

virtual bool shouldConsiderGEPOffsetSplit() const

AtomicExpansionKind

Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.

virtual InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const

TargetLowering(const TargetLowering &)=delete

virtual ArrayRef< MCPhysReg > getRoundingControlRegisters() const

Returns a 0 terminated array of rounding control registers that can be attached into strict FP call.

Primary interface to the complete machine description for the target machine.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

The instances of the Type class are immutable: once they are created, they are never changed.

LLVM Value Representation.

Base class of all SIMD vector types.

Define some predicates that are used for node matching.

bool isBitFieldInvertedMask(unsigned v)

const unsigned FPStatusBits

Definition ARMISelLowering.h:70

const unsigned FPReservedBits

Definition ARMISelLowering.h:74

Rounding

Possible values of current rounding mode, which is specified in bits 23:22 of FPSCR.

Definition ARMISelLowering.h:57

@ RN

Definition ARMISelLowering.h:58

@ RP

Definition ARMISelLowering.h:59

@ RZ

Definition ARMISelLowering.h:61

@ rmMask

Definition ARMISelLowering.h:62

@ RM

Definition ARMISelLowering.h:60

const unsigned RoundingBitsPos

Definition ARMISelLowering.h:66

FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ CXX_FAST_TLS

Used for access functions.

@ Fast

Attempts to make calls as fast as possible (e.g.

MemIndexedMode

MemIndexedMode enum - This enum defines the load / store indexed addressing modes.

CondCode

ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...

This namespace contains an enum with a value for every intrinsic/builtin function known by LLVM.

This is an optimization pass for GlobalISel generic memory operations.

bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State)

CCAssignFn - This function assigns a location for Val, updating State to reflect the change.

ComplexDeinterleavingOperation

VMOVModImmType

Definition ARMISelLowering.h:723

@ OtherModImm

Definition ARMISelLowering.h:727

@ VMVNModImm

Definition ARMISelLowering.h:725

@ MVEVMVNModImm

Definition ARMISelLowering.h:726

@ VMOVModImm

Definition ARMISelLowering.h:724

AtomicOrdering

Atomic ordering for LLVM's memory model.

ComplexDeinterleavingRotation

DWARFExpression::Operation Op

ArrayRef(const T &OneElt) -> ArrayRef< T >

This struct is a compact representation of a valid (non-zero power of two) alignment.

TypeSize getSizeInBits() const

Return the size of the specified value type in bits.

uint64_t getScalarSizeInBits() const

bool isVector() const

Return true if this is a vector value type.

bool isScalarInteger() const

Return true if this is an integer, but not a vector.

This structure contains all information that is necessary for lowering calls.