ARMInstPrinter.cpp Source File (original) (raw)

28#include

29#include

31using namespace llvm;

33#define DEBUG_TYPE "asm-printer"

35#define PRINT_ALIAS_INSTR

36#include "ARMGenAsmWriter.inc"

43 assert((imm & ~0x1f) == 0 && "Invalid shift encoding");

45 if (imm == 0)

46 return 32;

47 return imm;

48}

53 return;

54 O << ", ";

56 assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");

57 O << getShiftOpcStr(ShOpc);

60 O << " ";

63 }

64}

71 if (Opt == "reg-names-std") {

72 DefaultAltIdx = ARM::NoRegAltName;

73 return true;

74 }

75 if (Opt == "reg-names-raw") {

76 DefaultAltIdx = ARM::RegNamesRaw;

77 return true;

78 }

79 return false;

80}

89 unsigned Opcode = MI->getOpcode();

91 switch (Opcode) {

92 case ARM::VLLDM: {

94 O << '\t' << "vlldm" << '\t';

96 O << ", "

97 << "{d0 - d15}";

98 return;

99 }

100 case ARM::VLLDM_T2: {

101 const MCOperand &Reg = MI->getOperand(0);

102 O << '\t' << "vlldm" << '\t';

104 O << ", "

105 << "{d0 - d31}";

106 return;

107 }

108 case ARM::VLSTM: {

109 const MCOperand &Reg = MI->getOperand(0);

110 O << '\t' << "vlstm" << '\t';

112 O << ", "

113 << "{d0 - d15}";

114 return;

115 }

116 case ARM::VLSTM_T2: {

117 const MCOperand &Reg = MI->getOperand(0);

118 O << '\t' << "vlstm" << '\t';

120 O << ", "

121 << "{d0 - d31}";

122 return;

123 }

124

125 case ARM::MOVsr: {

126

127 const MCOperand &Dst = MI->getOperand(0);

128 const MCOperand &MO1 = MI->getOperand(1);

129 const MCOperand &MO2 = MI->getOperand(2);

130 const MCOperand &MO3 = MI->getOperand(3);

131

135

136 O << '\t';

138 O << ", ";

140

141 O << ", ";

145 return;

146 }

147

148 case ARM::MOVsi: {

149

150 const MCOperand &Dst = MI->getOperand(0);

151 const MCOperand &MO1 = MI->getOperand(1);

152 const MCOperand &MO2 = MI->getOperand(2);

153

157

158 O << '\t';

160 O << ", ";

162

165 return;

166 }

167

168 O << ", ";

172 return;

173 }

174

175

176 case ARM::STMDB_UPD:

177 case ARM::t2STMDB_UPD:

178 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {

179

180 O << '\t' << "push";

182 if (Opcode == ARM::t2STMDB_UPD)

183 O << ".w";

184 O << '\t';

187 return;

188 } else

189 break;

190

191 case ARM::STR_PRE_IMM:

192 if (MI->getOperand(2).getReg() == ARM::SP &&

193 MI->getOperand(3).getImm() == -4) {

194 O << '\t' << "push";

196 O << "\t{";

198 O << "}";

200 return;

201 } else

202 break;

203

204

205 case ARM::LDMIA_UPD:

206 case ARM::t2LDMIA_UPD:

207 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {

208

209 O << '\t' << "pop";

211 if (Opcode == ARM::t2LDMIA_UPD)

212 O << ".w";

213 O << '\t';

216 return;

217 } else

218 break;

219

220 case ARM::LDR_POST_IMM:

221 if (MI->getOperand(2).getReg() == ARM::SP &&

222 MI->getOperand(4).getImm() == 4) {

223 O << '\t' << "pop";

225 O << "\t{";

227 O << "}";

229 return;

230 } else

231 break;

232

233

234 case ARM::VSTMSDB_UPD:

235 case ARM::VSTMDDB_UPD:

236 if (MI->getOperand(0).getReg() == ARM::SP) {

237 O << '\t' << "vpush";

239 O << '\t';

242 return;

243 } else

244 break;

245

246

247 case ARM::VLDMSIA_UPD:

248 case ARM::VLDMDIA_UPD:

249 if (MI->getOperand(0).getReg() == ARM::SP) {

250 O << '\t' << "vpop";

252 O << '\t';

255 return;

256 } else

257 break;

258

259 case ARM::tLDMIA: {

260 bool Writeback = true;

261 MCRegister BaseReg = MI->getOperand(0).getReg();

262 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {

263 if (MI->getOperand(i).getReg() == BaseReg)

264 Writeback = false;

265 }

266

267 O << "\tldm";

268

270 O << '\t';

272 if (Writeback)

273 O << "!";

274 O << ", ";

277 return;

278 }

279

280

281

282

283

284

285

286 case ARM::LDREXD:

287 case ARM::STREXD:

288 case ARM::LDAEXD:

289 case ARM::STLEXD: {

291 bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD;

297

301 Reg, ARM::gsub_0, &MRI.getRegClass(ARM::GPRPairRegClassID)));

303

304

305 for (unsigned i = isStore ? 3 : 2; i < MI->getNumOperands(); ++i)

308 return;

309 }

310 break;

311 }

312 case ARM::TSB:

313 case ARM::t2TSB:

314 O << "\ttsb\tcsync";

315 return;

316 case ARM::t2DSB:

317 switch (MI->getOperand(0).getImm()) {

318 default:

321 break;

322 case 0:

323 O << "\tssbb";

324 break;

325 case 4:

326 O << "\tpssbb";

327 break;

328 }

330 return;

331 }

332

335

337}

338

342 if (Op.isReg()) {

345 } else if (Op.isImm()) {

347 } else {

348 assert(Op.isExpr() && "unknown operand kind in printOperand");

349 const MCExpr *Expr = Op.getExpr();

350 switch (Expr->getKind()) {

352 O << '#';

353 MAI.printExpr(O, *Expr);

354 break;

356

357

358

360 int64_t TargetAddress;

361 if ( Constant ->evaluateAsAbsolute(TargetAddress)) {

362 O << '#';

363 MAI.printExpr(O, *Expr);

364 } else {

365 O << "0x";

366 O.write_hex(static_cast<uint32_t>(TargetAddress));

367 }

368 break;

369 }

370 default:

371

372

373 MAI.printExpr(O, *Expr);

374 break;

375 }

376 }

377}

378

387 Target &= 0xffffffff;

391}

392

396 const MCOperand &MO1 = MI->getOperand(OpNum);

399 return;

400 }

401

403 O << "[pc, ";

404

405 int32_t OffImm = (int32_t)MO1.getImm();

406 bool isSub = OffImm < 0;

407

408

409 if (OffImm == INT32_MIN)

410 OffImm = 0;

411 if (isSub) {

413 } else {

415 }

416 O << "]";

417}

418

419

420

421

422

423

427 const MCOperand &MO1 = MI->getOperand(OpNum);

428 const MCOperand &MO2 = MI->getOperand(OpNum + 1);

429 const MCOperand &MO3 = MI->getOperand(OpNum + 2);

430

432

433

437 return;

438

439 O << ' ';

442}

443

447 const MCOperand &MO1 = MI->getOperand(OpNum);

448 const MCOperand &MO2 = MI->getOperand(OpNum + 1);

449

451

452

455}

456

457

458

459

460

467

469 O << "[";

471

474 O << ", ";

478 }

479 O << "]";

480 return;

481 }

482

483 O << ", ";

486

489 O << "]";

490}

491

497

499 O << "[";

501 O << ", ";

503 O << "]";

504}

505

512 O << "[";

514 O << ", ";

516 O << ", lsl ";

518 O << "]";

519}

520

525

526 if (!MO1.isReg()) {

528 return;

529 }

530

531#ifndef NDEBUG

535#endif

536

538}

539

541 unsigned OpNum,

544 const MCOperand &MO1 = MI->getOperand(OpNum);

545 const MCOperand &MO2 = MI->getOperand(OpNum + 1);

546

551 << ImmOffs;

552 return;

553 }

554

557

560}

561

562

563

564

565

568 bool AlwaysPrintImm0) {

572

574 O << '[';

576

580 O << ']';

581 return;

582 }

583

584

587

588 if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM::sub)) {

589 O << ", ";

591 }

592 O << ']';

593}

594

595template

600 if (!MO1.isReg()) {

602 return;

603 }

604

607 "unexpected idxmode");

609}

610

612 unsigned OpNum,

615 const MCOperand &MO1 = MI->getOperand(OpNum);

616 const MCOperand &MO2 = MI->getOperand(OpNum + 1);

617

621 return;

622 }

623

627 << ImmOffs;

628}

629

633 const MCOperand &MO = MI->getOperand(OpNum);

634 unsigned Imm = MO.getImm();

636 << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff);

637}

638

642 const MCOperand &MO1 = MI->getOperand(OpNum);

643 const MCOperand &MO2 = MI->getOperand(OpNum + 1);

644

645 O << (MO2.getImm() ? "" : "-");

647}

648

652 const MCOperand &MO = MI->getOperand(OpNum);

653 unsigned Imm = MO.getImm();

655 << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2);

656}

657

658template

662 const MCOperand &MO1 = MI->getOperand(OpNum);

663 const MCOperand &MO2 = MI->getOperand(OpNum + 1);

664

666 O << "[";

668 O << ", ";

670

671 if (shift > 0)

673

674 O << "]";

675}

676

684

685template

689 const MCOperand &MO1 = MI->getOperand(OpNum);

690 const MCOperand &MO2 = MI->getOperand(OpNum + 1);

691

692 if (!MO1.isReg()) {

694 return;

695 }

696

698 O << "[";

700

703 if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {

704 O << ", ";

707 }

708 O << "]";

709}

710

711template

715 const MCOperand &MO1 = MI->getOperand(OpNum);

716 const MCOperand &MO2 = MI->getOperand(OpNum+1);

717

718 if (!MO1.isReg()) {

720 return;

721 }

722

724 O << "[";

726

729 if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {

730 O << ", ";

733 << ImmOffs * 2;

734 }

735 O << "]";

736}

737

741 const MCOperand &MO1 = MI->getOperand(OpNum);

742 const MCOperand &MO2 = MI->getOperand(OpNum + 1);

743

745 O << "[";

748 O << ":" << (MO2.getImm() << 3);

749 }

750 O << "]";

751}

752

756 const MCOperand &MO1 = MI->getOperand(OpNum);

758 O << "[";

760 O << "]";

761}

762

764 unsigned OpNum,

767 const MCOperand &MO = MI->getOperand(OpNum);

769 O << "!";

770 else {

771 O << ", ";

773 }

774}

775

777 unsigned OpNum,

780 const MCOperand &MO = MI->getOperand(OpNum);

784 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");

786 O << ", ";

788}

789

793 unsigned val = MI->getOperand(OpNum).getImm();

795}

796

800 unsigned val = MI->getOperand(OpNum).getImm();

802}

803

807 unsigned val = MI->getOperand(OpNum).getImm();

809}

810

814 unsigned ShiftOp = MI->getOperand(OpNum).getImm();

815 bool isASR = (ShiftOp & (1 << 5)) != 0;

816 unsigned Amt = ShiftOp & 0x1f;

817 if (isASR) {

818 O << ", asr ";

820 } else if (Amt) {

821 O << ", lsl ";

823 }

824}

825

829 unsigned Imm = MI->getOperand(OpNum).getImm();

830 if (Imm == 0)

831 return;

832 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");

833 O << ", lsl ";

835}

836

840 unsigned Imm = MI->getOperand(OpNum).getImm();

841

842 if (Imm == 0)

843 Imm = 32;

844 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");

845 O << ", asr ";

847}

848

852 if (MI->getOpcode() != ARM::t2CLRM && MI->getOpcode() != ARM::VSCCLRMS) {

855 return MRI.getEncodingValue(LHS.getReg()) <

856 MRI.getEncodingValue(RHS.getReg());

857 }));

858 }

859

860 O << "{";

861 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {

862 if (i != OpNum)

863 O << ", ";

865 }

866 O << "}";

867}

868

872 MCRegister Reg = MI->getOperand(OpNum).getReg();

874 O << ", ";

876}

877

882 if (Op.getImm())

883 O << "be";

884 else

885 O << "le";

886}

887

893

897 unsigned IFlags = Op.getImm();

898 for (int i = 2; i >= 0; --i)

899 if (IFlags & (1 << i))

901

902 if (IFlags == 0)

903 O << "none";

904}

905

911 if (FeatureBits[ARM::FeatureMClass]) {

912

913 unsigned SYSm = Op.getImm() & 0xFFF;

914 unsigned Opcode = MI->getOpcode();

915

916

917 if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP]) {

919 if (TheReg && TheReg->isInRequiredFeatures({ARM::FeatureDSP})) {

920 O << TheReg->Name;

921 return;

922 }

923 }

924

925

926 SYSm &= 0xff;

927 if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) {

928

929

931 if (TheReg) {

932 O << TheReg->Name;

933 return;

934 }

935 }

936

938 if (TheReg) {

939 O << TheReg->Name;

940 return;

941 }

942

943 O << SYSm;

944

945 return;

946 }

947

948

949

950 unsigned SpecRegRBit = Op.getImm() >> 4;

951 unsigned Mask = Op.getImm() & 0xf;

952

953 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {

954 O << "APSR_";

955 switch (Mask) {

956 default:

958 case 4:

959 O << "g";

960 return;

961 case 8:

962 O << "nzcvq";

963 return;

964 case 12:

965 O << "nzcvqg";

966 return;

967 }

968 }

969

970 if (SpecRegRBit)

971 O << "SPSR";

972 else

973 O << "CPSR";

974

975 if (Mask) {

976 O << '_';

977 if (Mask & 8)

978 O << 'f';

979 if (Mask & 4)

980 O << 's';

981 if (Mask & 2)

982 O << 'x';

983 if (Mask & 1)

984 O << 'c';

985 }

986}

987

991 uint32_t Banked = MI->getOperand(OpNum).getImm();

992 auto TheReg = ARMBankedReg::lookupBankedRegByEncoding(Banked);

993 assert(TheReg && "invalid banked register operand");

994 std::string Name = TheReg->Name;

995

996 uint32_t isSPSR = (Banked & 0x20) >> 5;

997 if (isSPSR)

998 Name.replace(0, 4, "SPSR");

999 O << Name;

1000}

1001

1006

1007 if ((unsigned)CC == 15)

1008 O << "";

1011}

1012

1017 O << "cs";

1018 else

1020}

1021

1023 unsigned OpNum,

1028}

1029

1031 unsigned OpNum,

1036}

1037

1041 if (MI->getOperand(OpNum).getReg()) {

1042 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&

1043 "Expect ARM CPSR register!");

1044 O << 's';

1045 }

1046}

1047

1051 O << MI->getOperand(OpNum).getImm();

1052}

1053

1057 O << "p" << MI->getOperand(OpNum).getImm();

1058}

1059

1063 O << "c" << MI->getOperand(OpNum).getImm();

1064}

1065

1069 O << "{" << MI->getOperand(OpNum).getImm() << "}";

1070}

1071

1076

1077template

1081 const MCOperand &MO = MI->getOperand(OpNum);

1082

1085 return;

1086 }

1087

1088 int32_t OffImm = (int32_t)MO.getImm() << scale;

1089

1091 if (OffImm == INT32_MIN)

1092 O << "#-0";

1093 else if (OffImm < 0)

1094 O << "#-" << -OffImm;

1095 else

1096 O << "#" << OffImm;

1097}

1098

1103 << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4);

1104}

1105

1109 unsigned Imm = MI->getOperand(OpNum).getImm();

1111}

1112

1116

1117 unsigned Mask = MI->getOperand(OpNum).getImm();

1119 assert(NumTZ <= 3 && "Invalid IT mask!");

1120 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {

1121 if ((Mask >> Pos) & 1)

1122 O << 'e';

1123 else

1124 O << 't';

1125 }

1126}

1127

1133

1134 if (!MO1.isReg()) {

1136 return;

1137 }

1138

1140 O << "[";

1143 O << ", ";

1145 }

1146 O << "]";

1147}

1148

1150 unsigned Op,

1153 unsigned Scale) {

1156

1157 if (!MO1.isReg()) {

1159 return;

1160 }

1161

1163 O << "[";

1165 if (unsigned ImmOffs = MO2.getImm()) {

1166 O << ", ";

1168 }

1169 O << "]";

1170}

1171

1178

1185

1192

1198

1199

1200

1201

1202

1206 const MCOperand &MO1 = MI->getOperand(OpNum);

1207 const MCOperand &MO2 = MI->getOperand(OpNum + 1);

1208

1211

1212

1213 assert(MO2.isImm() && "Not a valid t2_so_reg value!");

1216}

1217

1218template

1222 const MCOperand &MO1 = MI->getOperand(OpNum);

1223 const MCOperand &MO2 = MI->getOperand(OpNum + 1);

1224

1225 if (!MO1.isReg()) {

1227 return;

1228 }

1229

1231 O << "[";

1233

1234 int32_t OffImm = (int32_t)MO2.getImm();

1235 bool isSub = OffImm < 0;

1236

1237 if (OffImm == INT32_MIN)

1238 OffImm = 0;

1239 if (isSub) {

1240 O << ", ";

1242 } else if (AlwaysPrintImm0 || OffImm > 0) {

1243 O << ", ";

1245 }

1246 O << "]";

1247}

1248

1249template

1251 unsigned OpNum,

1254 const MCOperand &MO1 = MI->getOperand(OpNum);

1255 const MCOperand &MO2 = MI->getOperand(OpNum + 1);

1256

1258 O << "[";

1260

1261 int32_t OffImm = (int32_t)MO2.getImm();

1262 bool isSub = OffImm < 0;

1263

1264 if (OffImm == INT32_MIN)

1265 OffImm = 0;

1266 if (isSub) {

1267 O << ", ";

1269 } else if (AlwaysPrintImm0 || OffImm > 0) {

1270 O << ", ";

1272 }

1273 O << "]";

1274}

1275

1276template

1278 unsigned OpNum,

1281 const MCOperand &MO1 = MI->getOperand(OpNum);

1282 const MCOperand &MO2 = MI->getOperand(OpNum + 1);

1283

1284 if (!MO1.isReg()) {

1286 return;

1287 }

1288

1290 O << "[";

1292

1293 int32_t OffImm = (int32_t)MO2.getImm();

1294 bool isSub = OffImm < 0;

1295

1296 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");

1297

1298

1299 if (OffImm == INT32_MIN)

1300 OffImm = 0;

1301 if (isSub) {

1302 O << ", ";

1304 } else if (AlwaysPrintImm0 || OffImm > 0) {

1305 O << ", ";

1307 }

1308 O << "]";

1309}

1310

1314 const MCOperand &MO1 = MI->getOperand(OpNum);

1315 const MCOperand &MO2 = MI->getOperand(OpNum + 1);

1316

1318 O << "[";

1321 O << ", ";

1323 }

1324 O << "]";

1325}

1326

1330 const MCOperand &MO1 = MI->getOperand(OpNum);

1331 int32_t OffImm = (int32_t)MO1.getImm();

1332 O << ", ";

1334 if (OffImm == INT32_MIN)

1335 O << "#-0";

1336 else if (OffImm < 0)

1337 O << "#-" << -OffImm;

1338 else

1339 O << "#" << OffImm;

1340}

1341

1345 const MCOperand &MO1 = MI->getOperand(OpNum);

1346 int32_t OffImm = (int32_t)MO1.getImm();

1347

1348 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");

1349

1350 O << ", ";

1352 if (OffImm == INT32_MIN)

1353 O << "#-0";

1354 else if (OffImm < 0)

1355 O << "#-" << -OffImm;

1356 else

1357 O << "#" << OffImm;

1358}

1359

1361 unsigned OpNum,

1364 const MCOperand &MO1 = MI->getOperand(OpNum);

1365 const MCOperand &MO2 = MI->getOperand(OpNum + 1);

1366 const MCOperand &MO3 = MI->getOperand(OpNum + 2);

1367

1369 O << "[";

1371

1372 assert(MO2.getReg() && "Invalid so_reg load / store address!");

1373 O << ", ";

1375

1376 unsigned ShAmt = MO3.getImm();

1377 if (ShAmt) {

1378 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");

1379 O << ", lsl ";

1381 }

1382 O << "]";

1383}

1384

1388 const MCOperand &MO = MI->getOperand(OpNum);

1390}

1391

1395 unsigned EncodedImm = MI->getOperand(OpNum).getImm();

1396 unsigned EltBits;

1398

1400 O << "#0x";

1401 O.write_hex(Val);

1402}

1403

1407 unsigned Imm = MI->getOperand(OpNum).getImm();

1409}

1410

1414 unsigned Imm = MI->getOperand(OpNum).getImm();

1415 if (Imm == 0)

1416 return;

1417 assert(Imm <= 3 && "illegal ror immediate!");

1418 O << ", ror ";

1420}

1421

1426

1427

1428 if (Op.isExpr())

1430

1431 unsigned Bits = Op.getImm() & 0xFF;

1432 unsigned Rot = (Op.getImm() & 0xF00) >> 7;

1433

1434 bool PrintUnsigned = false;

1435 switch (MI->getOpcode()) {

1436 case ARM::MOVi:

1437

1438 PrintUnsigned = (MI->getOperand(OpNum - 1).getReg() == ARM::PC);

1439 break;

1440 case ARM::MSRi:

1441

1442 PrintUnsigned = true;

1443 break;

1444 }

1445

1448

1449 O << "#";

1450 if (PrintUnsigned)

1452 else

1454 return;

1455 }

1456

1457

1458 O << "#";

1460 O << ", #";

1462}

1463

1468

1473

1477 O << "[" << MI->getOperand(OpNum).getImm() << "]";

1478}

1479

1483 O << "{";

1485 O << "}";

1486}

1487

1491 MCRegister Reg = MI->getOperand(OpNum).getReg();

1492 MCRegister Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);

1493 MCRegister Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);

1494 O << "{";

1496 O << ", ";

1498 O << "}";

1499}

1500

1504 MCRegister Reg = MI->getOperand(OpNum).getReg();

1505 MCRegister Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);

1506 MCRegister Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);

1507 O << "{";

1509 O << ", ";

1511 O << "}";

1512}

1513

1517

1518

1519

1520 O << "{";

1522 O << ", ";

1523 printRegName(O, MI->getOperand(OpNum).getReg() + 1);

1524 O << ", ";

1525 printRegName(O, MI->getOperand(OpNum).getReg() + 2);

1526 O << "}";

1527}

1528

1532

1533

1534

1535 O << "{";

1537 O << ", ";

1538 printRegName(O, MI->getOperand(OpNum).getReg() + 1);

1539 O << ", ";

1540 printRegName(O, MI->getOperand(OpNum).getReg() + 2);

1541 O << ", ";

1542 printRegName(O, MI->getOperand(OpNum).getReg() + 3);

1543 O << "}";

1544}

1545

1547 unsigned OpNum,

1550 O << "{";

1552 O << "[]}";

1553}

1554

1556 unsigned OpNum,

1559 MCRegister Reg = MI->getOperand(OpNum).getReg();

1560 MCRegister Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);

1561 MCRegister Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);

1562 O << "{";

1564 O << "[], ";

1566 O << "[]}";

1567}

1568

1570 unsigned OpNum,

1573

1574

1575

1576 O << "{";

1578 O << "[], ";

1579 printRegName(O, MI->getOperand(OpNum).getReg() + 1);

1580 O << "[], ";

1581 printRegName(O, MI->getOperand(OpNum).getReg() + 2);

1582 O << "[]}";

1583}

1584

1586 unsigned OpNum,

1589

1590

1591

1592 O << "{";

1594 O << "[], ";

1595 printRegName(O, MI->getOperand(OpNum).getReg() + 1);

1596 O << "[], ";

1597 printRegName(O, MI->getOperand(OpNum).getReg() + 2);

1598 O << "[], ";

1599 printRegName(O, MI->getOperand(OpNum).getReg() + 3);

1600 O << "[]}";

1601}

1602

1606 MCRegister Reg = MI->getOperand(OpNum).getReg();

1607 MCRegister Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);

1608 MCRegister Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);

1609 O << "{";

1611 O << "[], ";

1613 O << "[]}";

1614}

1615

1619

1620

1621

1622 O << "{";

1624 O << "[], ";

1625 printRegName(O, MI->getOperand(OpNum).getReg() + 2);

1626 O << "[], ";

1627 printRegName(O, MI->getOperand(OpNum).getReg() + 4);

1628 O << "[]}";

1629}

1630

1634

1635

1636

1637 O << "{";

1639 O << "[], ";

1640 printRegName(O, MI->getOperand(OpNum).getReg() + 2);

1641 O << "[], ";

1642 printRegName(O, MI->getOperand(OpNum).getReg() + 4);

1643 O << "[], ";

1644 printRegName(O, MI->getOperand(OpNum).getReg() + 6);

1645 O << "[]}";

1646}

1647

1649 unsigned OpNum,

1652

1653

1654

1655 O << "{";

1657 O << ", ";

1658 printRegName(O, MI->getOperand(OpNum).getReg() + 2);

1659 O << ", ";

1660 printRegName(O, MI->getOperand(OpNum).getReg() + 4);

1661 O << "}";

1662}

1663

1667

1668

1669

1670 O << "{";

1672 O << ", ";

1673 printRegName(O, MI->getOperand(OpNum).getReg() + 2);

1674 O << ", ";

1675 printRegName(O, MI->getOperand(OpNum).getReg() + 4);

1676 O << ", ";

1677 printRegName(O, MI->getOperand(OpNum).getReg() + 6);

1678 O << "}";

1679}

1680

1681template

1685 MCRegister Reg = MI->getOperand(OpNum).getReg();

1686 const char *Prefix = "{";

1687 for (unsigned i = 0; i < NumRegs; i++) {

1688 O << Prefix;

1690 Prefix = ", ";

1691 }

1692 O << "}";

1693}

1694

1695template<int64_t Angle, int64_t Remainder>

1699 unsigned Val = MI->getOperand(OpNo).getImm();

1700 O << "#" << (Val * Angle) + Remainder;

1701}

1702

1710

1714

1715 unsigned Mask = MI->getOperand(OpNum).getImm();

1717 assert(NumTZ <= 3 && "Invalid VPT mask!");

1718 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {

1719 bool T = ((Mask >> Pos) & 1) == 0;

1720 if (T)

1721 O << 't';

1722 else

1723 O << 'e';

1724 }

1725}

1726

1730 uint32_t Val = MI->getOperand(OpNum).getImm();

1731 assert(Val <= 1 && "Invalid MVE saturate operand");

1732 O << "#" << (Val == 1 ? 48 : 64);

1733}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static bool isStore(int Opcode)

static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, unsigned ShImm, ARMInstPrinter &printer)

Definition ARMInstPrinter.cpp:50

static unsigned translateShiftImm(unsigned imm)

translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.

Definition ARMInstPrinter.cpp:41

static uint64_t scale(uint64_t Num, uint32_t N, uint32_t D)

static MCRegister getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)

void printT2AddrModeImm0_1020s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1311

void printMVEVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1682

void printVectorListTwoAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1555

void printCPSIFlag(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:894

void printSBitModifierOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1038

void printVectorListFour(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1529

void printThumbAddrModeImm5S1Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1172

void printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:837

void printVPTPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1703

void printInstSyncBOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:797

void printAddrMode7Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:753

void printRegisterList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:849

void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:339

void printSORegRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:424

void printComplexRotationOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1696

void printMveSaturateOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1727

void printVectorListTwo(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1488

void printFBits16(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1464

ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)

Definition ARMInstPrinter.cpp:66

void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:461

void printPCLabel(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1072

void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:611

void printCPSIMod(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:888

void printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1501

void printT2AddrModeImm8Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1250

bool applyTargetSpecificCLOption(StringRef Opt) override

Customize the printer according to a command line option.

Definition ARMInstPrinter.cpp:70

virtual bool printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)

void printThumbAddrModeImm5S4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1186

void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:596

void printMveAddrModeRQOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:659

void printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:393

void printVectorListTwoSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1603

void printT2SOOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1203

void printAddrModeTBB(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:492

void printVectorListOne(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1480

void printThumbITMask(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1113

void printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:630

void printAddrMode6OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:763

void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:686

void printVectorListThreeSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1648

void printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1404

void printTraceSyncBOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:804

void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)

void printPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1002

void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:521

void printGPRPairOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:869

void printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1342

void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1193

void printVectorListFourAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1585

void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:776

void printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:649

void printCImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1060

void printRegName(raw_ostream &OS, MCRegister Reg) override

Print the assembler register name.

Definition ARMInstPrinter.cpp:82

void printFBits32(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1469

void printVectorListThreeAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1569

void printRotImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1411

void printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1022

void printMemBOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:790

void printVectorListThreeSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1616

void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override

Print the specified MCInst to the specified raw_ostream.

Definition ARMInstPrinter.cpp:86

void printPostIdxRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:639

static const char * getRegisterName(MCRegister Reg, unsigned AltIdx=ARM::NoRegAltName)

void printFPImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1385

void printT2AddrModeImm8OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1327

void printCoprocOptionImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1066

void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1128

void printT2AddrModeSoRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1360

void printShiftImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:811

void printMSRMaskOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:906

void printT2AddrModeImm8s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1277

void printSORegImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:444

void printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:826

void printBankedRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:988

void printThumbSRImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1106

void printModImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1422

void printSetendOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:878

void printVectorListOneAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1546

void printThumbAddrModeImm5S2Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1179

void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:540

void printAddrMode6Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:738

void printMandatoryRestrictedPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1013

void printVectorListFourSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1631

void printPImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1054

void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1099

void printVPTMask(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1711

void printVectorListThree(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1514

void printVectorListFourSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1664

void printVMOVModImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1392

void printAdrLabelOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1078

void printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1219

void printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, raw_ostream &O, bool AlwaysPrintImm0)

Definition ARMInstPrinter.cpp:566

void printThumbAddrModeImm5SOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O, unsigned Scale)

Definition ARMInstPrinter.cpp:1149

void printAddrModeTBH(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:506

void printNoHashImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1048

void printVectorIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1474

void printLdStmModeOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:677

void printAddrMode5FP16Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:712

void printMandatoryInvertedPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)

Definition ARMInstPrinter.cpp:1030

This is an important base class in LLVM.

Container class for subtarget features.

This class is intended to be used as a base class for asm properties and features specific to the tar...

Base class for the full range of assembler expressions which are needed for parsing.

@ Constant

Constant expressions.

@ Binary

Binary expressions.

WithMarkup markup(raw_ostream &OS, Markup M)

format_object< int64_t > formatHex(int64_t Value) const

raw_ostream * CommentStream

A stream that comments can be emitted to if desired.

const MCRegisterInfo & MRI

void printAnnotation(raw_ostream &OS, StringRef Annot)

Utility function for printing annotations.

format_object< int64_t > formatImm(int64_t Value) const

Utility function to print immediates in decimal or hex.

bool getUseMarkup() const

bool PrintBranchImmAsAddress

If true, a branch immediate (e.g.

MCInstPrinter(const MCAsmInfo &mai, const MCInstrInfo &mii, const MCRegisterInfo &mri)

Instances of this class represent a single low-level machine instruction.

void addOperand(const MCOperand Op)

void setOpcode(unsigned Op)

Interface to description of machine instruction set.

Instances of this class represent operands of the MCInst class.

static MCOperand createReg(MCRegister Reg)

MCRegister getReg() const

Returns the register number.

const MCExpr * getExpr() const

MCRegisterClass - Base class of TargetRegisterClass.

bool contains(MCRegister Reg) const

contains - Return true if the specified register is included in this register class.

MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...

Wrapper class representing physical registers. Should be passed by value.

Generic base class for all target subtargets.

bool hasFeature(unsigned Feature) const

const FeatureBitset & getFeatureBits() const

StringRef - Represent a constant reference to a string, i.e.

This class implements an extremely fast bulk output stream that can only output to a stream.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

static CondCodes getOppositeCondition(CondCodes CC)

const MClassSysReg * lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm)

const MClassSysReg * lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm)

const MClassSysReg * lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm)

unsigned char getAM3Offset(unsigned AM3Opc)

unsigned char getAM5FP16Offset(unsigned AM5Opc)

unsigned getSORegOffset(unsigned Op)

int getSOImmVal(unsigned Arg)

getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...

ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)

uint64_t decodeVMOVModImm(unsigned ModImm, unsigned &EltBits)

decodeVMOVModImm - Decode a NEON/MVE modified immediate value into the element value and the element ...

unsigned getAM2IdxMode(unsigned AM2Opc)

unsigned getAM3IdxMode(unsigned AM3Opc)

unsigned getAM2Offset(unsigned AM2Opc)

const char * getAMSubModeStr(AMSubMode Mode)

float getFPImmFloat(unsigned Imm)

ShiftOpc getSORegShOp(unsigned Op)

AddrOpc getAM5Op(unsigned AM5Opc)

AddrOpc getAM5FP16Op(unsigned AM5Opc)

const char * getAddrOpcStr(AddrOpc Op)

StringRef getShiftOpcStr(ShiftOpc Op)

unsigned char getAM5Offset(unsigned AM5Opc)

AddrOpc getAM2Op(unsigned AM2Opc)

AddrOpc getAM3Op(unsigned AM3Opc)

AMSubMode getAM4SubMode(unsigned Mode)

static const char * InstSyncBOptToString(unsigned val)

static const char * MemBOptToString(unsigned val, bool HasV8)

uint64_t evaluateBranchTarget(const MCInstrDesc &InstDesc, uint64_t Addr, int64_t Imm)

static const char * IModToString(unsigned val)

static const char * IFlagsToString(unsigned val)

static const char * TraceSyncBOptToString(unsigned val)

This is an optimization pass for GlobalISel generic memory operations.

auto drop_begin(T &&RangeOrContainer, size_t N=1)

Return a range covering RangeOrContainer with the first N elements excluded.

static const char * ARMVPTPredToString(ARMVCC::VPTCodes CC)

constexpr T rotr(T V, int R)

int bit_width(T Value)

Returns the number of bits needed to represent Value if Value is nonzero.

int countr_zero(T Val)

Count number of 0's from the least significant bit to the most stopping at the first 1.

bool is_sorted(R &&Range, Compare C)

Wrapper function around std::is_sorted to check if elements in a range R are sorted with respect to a...

DWARFExpression::Operation Op

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

static const char * ARMCondCodeToString(ARMCC::CondCodes CC)